Specification Sheet

Processor Graphics Registers
130 Datasheet, Volume 2 of 2
4.31 Power Management Capabilities ID (PMCAPID)—
Offset D0h
This register contains the PCI Power Management Capability ID and the next capability
pointer.
Access Method
Default: 1h
Bit
Range
Default &
Access
Field Name (ID): Description
15:0
0h
RW
MESSDATA: Base message data pattern assigned by system software and used to
handle an MSI from the device.
When the device should generate an interrupt request, it writes a 32-bit value to the
memory address specified in the MA register. The upper 16 bits are always set to 0.
The lower 16 bits are supplied by this register.
Type: CFG
(Size: 16 bits)
Offset: [B:0, D:2, F:0] + D0h
15 12 8 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
NEXT_PTR
CAP_ID
Bit
Range
Default &
Access
Field Name (ID): Description
15:8
0h
RO
NEXT_PTR: This contains a pointer to the next item in the capabilities list. This is the
final capability in the list and should be set to 00h.
7:0
1h
RO
CAP_ID: SIG defines this ID is 01h for power management.