Specification Sheet

Processor Graphics Registers
128 Datasheet, Volume 2 of 2
4.28 Message Control (MC)—Offset AEh
Message Signaled Interrupt control register. System software can modify bits in this
register, but the device is prohibited from doing so. If the device writes the same
message multiple times, only one of those messages is guaranteed to be serviced. If all
of them should be serviced, the device should not generate the same message again
until the driver services the earlier one.
Access Method
Default: 0h
Bit
Range
Default &
Access
Field Name (ID): Description
15:8
D0h
RO
POINTNEXT: This contains a pointer to the next item in the capabilities list which is
the Power Management capability.
7:0
5h
RO
CAPID: Value of 05h identifies this linked list item (capability structure) as being for
MSI registers.
Type: CFG
(Size: 16 bits)
Offset: [B:0, D:2, F:0] + AEh
15 12 8 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSVD
CAP64B
MME
MMC
MSIEN
Bit
Range
Default &
Access
Field Name (ID): Description
15:8
0h
RO
Reserved (RSVD): Reserved.
7
0h
RO
CAP64B: Hardwired to 0 to indicate that the function does not implement the upper
32 bits of the Message address register and is incapable of generating a 64-bit
memory address.
6:4
0h
RW
MME: System software programs this field to indicate the actual number of messages
allocated to this device. This number will be equal to or less than the number actually
requested.
The encoding is the same as for the MMC field below.
3:1
0h
RO
MMC: System Software reads this field to determine the number of messages being
requested by this device.
000:1
All of the following are reserved in this implementation
001:2
010:4
011:8
100:16
101:32
110:Reserved
111:Reserved
0
0h
RW
MSIEN: Controls the ability of this device to generate MSIs.