Specification Sheet

Datasheet, Volume 2 of 2 127
Processor Graphics Registers
4.26 PCI Express Capability Header (PCIECAPHDR)—
Offset 70h
This is the header register for the PCI Express Capability Structure, allowing the
exposure of PCI Express Extended Capabilities which are required for SVM OS support.
Access Method
Default: AC10h
4.27 Message Signaled Interrupts Capability ID
(MSI)—Offset ACh
When a device supports MSI it can generate an interrupt request to the processor by
writing a predefined data item (a message) to a predefined memory address. The
reporting of the existence of this capability can be disabled by setting MSICH (CAPL[0]
@ 7Fh). In that case walking this linked list will skip this capability and instead go
directly to the PCI PM capability.
Access Method
Default: D005h
Type: CFG
(Size: 16 bits)
Offset: [B:0, D:2, F:0] + 70h
15 12 8 4 0
1 0 1 0 1 1 0 0 0 0 0 1 0 0 0 0
NEXT_CAP
CAP_ID
Bit
Range
Default &
Access
Field Name (ID): Description
15:8
ACh
RO
NEXT_CAP: This field contains the offset to the next PCI Capability structure, the MSI
Capabilities at ACh
7:0
10h
RO
CAP_ID: Indicates the PCI Express Capability structure. This field should return a
Capability ID of 10h indicating that this is a PCI Express Capability structure
Type: CFG
(Size: 16 bits)
Offset: [B:0, D:2, F:0] + ACh
15 12 8 4 0
1 1 0 1 0 0 0 0 0 0 0 0 0 1 0 1
POINTNEXT
CAPID