Specification Sheet

Datasheet, Volume 2 of 2 11
13.15 Memory Base Address (MBASE)—Offset 20h ....................................................... 403
13.16 Memory Limit Address (MLIMIT)—Offset 22h....................................................... 403
13.17 Prefetchable Memory Base Address (PMBASE)—Offset 24h.................................... 404
13.18 Prefetchable Memory Limit Address (PMLIMIT)—Offset 26h ................................... 405
13.19 Prefetchable Memory Base Address Upper (PMBASEU)—Offset 28h ........................ 406
13.20 Prefetchable Memory Limit Address Upper (PMLIMITU)—Offset 2Ch........................ 407
13.21 Capabilities Pointer (CAPPTR)—Offset 34h........................................................... 408
13.22 Interrupt Line (INTRLINE)—Offset 3Ch ............................................................... 408
13.23 Interrupt Pin (INTRPIN)—Offset 3Dh .................................................................. 409
13.24 Bridge Control (BCTRL)—Offset 3Eh ................................................................... 409
13.25 Power Management Capabilities (PM)—Offset 80h................................................ 411
13.26 Power Management Control/Status (PM)—Offset 84h ........................................... 412
13.27 Subsystem ID and Vendor ID Capabilities (SS)—Offset 88h................................... 413
13.28 Subsystem ID and Subsystem Vendor ID (SS)—Offset 8Ch ................................... 414
13.29 Message Signaled Interrupts Capability ID (MSI)—Offset 90h ................................ 415
13.30 Message Control (MC)—Offset 92h..................................................................... 415
13.31 Message Address (MA)—Offset 94h.................................................................... 416
13.32 Message Data (MD)—Offset 98h ........................................................................ 417
13.33 PCI Express-G Capability List (PEG)—Offset A0h .................................................. 417
13.34 PCI Express-G Capabilities (PEG)—Offset A2h ..................................................... 418
13.35 Device Capabilities (DCAP)—Offset A4h .............................................................. 418
13.36 Device Control (DCTL)—Offset A8h .................................................................... 419
13.37 Device Status (DSTS)—Offset AAh ..................................................................... 420
13.38 Link Capability (LCAP)—Offset ACh .................................................................... 421
13.39 Link Control (LCTL)—Offset B0h ........................................................................ 423
13.40 Link Status (LSTS)—Offset B2h ......................................................................... 424
13.41 Slot Capabilities (SLOTCAP)—Offset B4h............................................................. 426
13.42 Slot Control (SLOTCTL)—Offset B8h................................................................... 427
13.43 Slot Status (SLOTSTS)—Offset BAh.................................................................... 429
13.44 Root Control (RCTL)—Offset BCh ....................................................................... 430
13.45 Root Status (RSTS)—Offset C0h ........................................................................ 431
13.46 Device Capabilities 2 (DCAP2)—Offset C4h.......................................................... 432
13.47 Device Control 2 (DCTL2)—Offset C8h................................................................ 434
13.48 Link Control 2 (LCTL2)—Offset D0h.................................................................... 435
13.49 Link Status 2 (LSTS2)—Offset D2h .................................................................... 437
13.50 Port VC Capability Register 1 (PVCCAP1)—Offset 104h ......................................... 438
13.51 Port VC Capability Register 2 (PVCCAP2)—Offset 108h ......................................... 439
13.52 Port VC Control (PVCCTL)—Offset 10Ch .............................................................. 439
13.53 VC0 Resource Capability (VC0RCAP)—Offset 110h ............................................... 440
13.54 VC0 Resource Control (VC0RCTL)—Offset 114h ................................................... 441
13.55 VC0 Resource Status (VC0RSTS)—Offset 11Ah .................................................... 442
13.56 PEG Uncorrectable Error Status—Offset 1C4h ...................................................... 443
13.57 PEG Uncorrectable Error Mask—Offset 1C8h........................................................ 444
13.58 PEG Uncorrectable Error Severity—Offset 1CCh ................................................... 444
13.59 PEG Correctable Error Status—Offset 1D0h ......................................................... 445
13.60 PEG Correctable Error Mask—Offset 1D4h ........................................................... 446
13.61 PEG Advanced Error Capabilities and Control—Offset 1D8h.................................... 446
13.62 PEG Header Log—Offset 1DCh, 1E0h, 1E4h, 1E8h ................................................ 447
13.63 PEG Root Error Command—Offset 1ECh.............................................................. 447
13.64 PEG Root Error Status—Offset 1F0h ................................................................... 448
13.65 PEG Error Source Identification—Offset 1F4h....................................................... 448
14 PCI Express* Controller (x4) Registers.................................................................. 449
14.1 Vendor Identification (VID)—Offset 0h ............................................................... 451
14.2 Device Identification (DID)—Offset 2h................................................................ 451