Specification Sheet

Datasheet, Volume 2 of 2 125
Processor Graphics Registers
4.25 Multi Size Aperture Control (MSAC)—Offset 62h
This register determines the size of the graphics memory aperture in function 0 and in
the trusted space. Only the system BIOS will write this register based on pre- boot
address allocation efforts, but the graphics may read this register to determine the
correct aperture size. System BIOS needs to save this value on boot so that it can reset
it correctly during S3 resume.
This register is Intel TXT locked, becomes read-only when trusted environment is
launched.
Access Method
Default: 1h
Bit
Range
Default &
Access
Field Name (ID): Description
31:20
0h
RO_V
BDSM: This register contains bits 31 to 20 of the base address of stolen DRAM
memory. BIOS determines the base of graphics stolen memory by subtracting the
graphics stolen memory size (PCI Device 0 offset 50 bits 15:8) from TOLUD (PCI
Device 0, offset BC, bits 31:20).
19:1
0h
RO
Reserved (RSVD): Reserved.
0
0h
RO_V
LOCK: This bit will lock all writeable settings in this register, including itself.
Type: CFG
(Size: 8 bits)
Offset: [B:0, D:2, F:0] + 62h
7 4 0
0 0 0 0 0 0 0 1
RSVDRW
APSZ4 APSZ3 APSZ2 APSZ1 APSZ0
Bit
Range
Default &
Access
Field Name (ID): Description
7:5
0h
RW
RSVDRW: Scratch Bits Only -- Have no physical effect on hardware
4
0h
RW_KV
APSZ4: This field is used in conjunction with other APSZ* fields to determine the size
of Aperture (GMADR) and affects certain bits of GMADR register. The description below
is for all APSZ* fields 4:0 -
00000 = 128MB => GMADR.B[26:4] is hardwired to 0
00001 = 256MB => GMADR.B[27] = 0, RO
00010 = illegal (hardware will treat this as 00011)
00011 = 512MB => GMADR.B[28:27] = 0, RO
0100-00110 = illegal (hardware will treat this as 00111)
00111= 1024MB => GMADR.B[29:27] = 0, RO
000-01110 = illegal (hardware will treat this as 01111)
01111= 2048MB => GMADR.B[30:27] = 0, RO
10000-11110 = illegal (hardware will treat this as 11111)
11111 = 4096MB => GMADR.B[31:27] = 0, RO