Specification Sheet

Processor Graphics Registers
124 Datasheet, Volume 2 of 2
4.24 Base Data of Stolen Memory (BDSM)—Offset 5Ch
This register contains the base address of graphics data stolen DRAM memory. BIOS
determines the base of graphics data stolen memory by subtracting the graphics data
stolen memory size (PCI Device 0 offset 52 bits 7:4) from TOLUD (PCI Device 0 offset
BC bits 31:20).
Access Method
Default: 0h
6
0h
RO
Reserved (RSVD): Reserved.
5
1h
RO_V
D3EN:
0: Bus 0 Device 3 is disabled and hidden
1: Bus 0 Device 3 is enabled and visible
This bit will be set to 0b and remain 0b if Device 3 capability is disabled.
4
1h
RO_V
D2EN:
0: Bus 0 Device 2 is disabled and hidden
1: Bus 0 Device 2 is enabled and visible
This bit will be set to 0b and remain 0b if Device 2 capability is disabled.
3
1h
RO_V
D1F0EN:
0: Bus 0 Device 1 Function 0 is disabled and hidden.
1: Bus 0 Device 1 Function 0 is enabled and visible.
This bit will be set to 0b and remain 0b if PEG10 capability is disabled.
2
1h
RO_V
D1F1EN:
0: Bus 0 Device 1 Function 1 is disabled and hidden.
1: Bus 0 Device 1 Function 1 is enabled and visible.
This bit will be set to 0b and remain 0b if:
- PEG11 capability is disabled by fuses, OR
- PEG11 is disabled by strap (PEG0CFGSEL)
1
1h
RO_V
D1F2EN:
0: Bus 0 Device 1 Function 2 is disabled and hidden.
1: Bus 0 Device 1 Function 2 is enabled and visible.
This bit will be set to 0b and remain 0b if:
- PEG12 capability is disabled by fuses, OR
- PEG12 is disabled by strap (PEG0CFGSEL)
0
1h
RO
D0EN: Bus 0 Device 0 Function 0 may not be disabled and is therefore hardwired to 1.
Bit
Range
Default &
Access
Field Name (ID): Description
Type: CFG
(Size: 32 bits)
Offset: [B:0, D:2, F:0] + 5Ch
3
1
2
8
2
4
2
0
1
6
1
2
8 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BDSM
RSVD
LOCK