Specification Sheet
Datasheet, Volume 2 of 2 121
Processor Graphics Registers
4.22 Capabilities B (CAPID0)—Offset 48h
Control of bits in this register are only required for customer visible SKU differentiation.
Access Method
Default: 0h
Type: CFG
(Size: 32 bits)
Offset: [B:0, D:2, F:0] + 48h
3
1
2
8
2
4
2
0
1
6
1
2
8
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IMGU_DIS
RSVD
SMT
CACHESZ
RSVD
PLL_REF100_CFG
PEGG3_DIS
RSVD
ADDGFXEN
ADDGFXCAP
RSVD
DMIG3DIS
RSVD
GMM_DIS
RSVD
DMFC_DDR3
RSVD
LPDDR3_EN
RSVD
Bit
Range
Default &
Access
Field Name (ID): Description
31
0h
RO_V
IMGU_DIS:
0: Device 5 associated memory spaces are accessible.
1: Device 5 associated memory and IO spaces are disabled by hardwiring the D1F2EN
field, bit 1 of the Device Enable register, (DEVEN Dev 0 Offset 54h) to '0'.
30:29
0h
RO
Reserved (RSVD): Reserved.
28
0h
RO_V
SMT: This setting indicates whether or not the Processor is SMT capable.
27:25
0h
RO_V
CACHESZ: This setting indicates the supporting cache sizes.
24
0h
RO
Reserved (RSVD): Reserved.
23:21
0h
RO_V
PLL_REF100_CFG: DDR3 Maximum Frequency Capability with 100 Memory.
hardware will update this field with the value of FUSE_PLL_REF100_CFG and then
apply SSKU overrides.
Maximum allowed memory frequency with 100 MHz ref clk. Also serves as defeature.
Unlike 133 MHz ref fuses, these are normal 3 bit field
0: 100 MHz ref disabled
1: up to DDR-1400 (7 x 200)
2: up to DDR-1600 (8 x 200)
3: up to DDR-1800 (8 x 200)
4: up to DDR-2000 (10 x 200)
5: up to DDR-2200 (11 x 200)
6: up to DDR-2400 (12 x 200)
7: no limit (but still limited by _DDR_FREQ200 to 2600)