Specification Sheet

Processor Graphics Registers
120 Datasheet, Volume 2 of 2
4.21 Capabilities A (CAPID0)—Offset 44h
Control of bits in this register are only required for customer visible SKU differentiation.
Access Method
Default: 0h
Type: CFG
(Size: 32 bits)
Offset: [B:0, D:2, F:0] + 44h
3
1
2
8
2
4
2
0
1
6
1
2
8 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSVD
ECCDIS
RSVD
VTDD
RSVD
DDPCD
X2APIC_EN
PDCD
RSVD
Bit
Range
Default &
Access
Field Name (ID): Description
31:26
0h
RO
Reserved (RSVD): Reserved.
25
0h
RO_V
ECCDIS:
0b ECC capable
1b Not ECC capable
24
0h
RO
Reserved (RSVD): Reserved.
23
0h
RO_V
VTDD:
0: Enable VTd
1: Disable VTd
22:15
0h
RO
Reserved (RSVD): Reserved.
14
0h
RO_V
DDPCD: Allows Dual Channel operation but only supports 1 DIMM per channel.
0: 2 DIMMs per channel enabled
1: 2 DIMMs per channel disabled. This setting hardwires bits 2 and 3 of the rank
population field for each channel to zero. (MCHBAR offset 260h, bits 22-23 for channel
0 and MCHBAR offset 660h, bits 22-23 for channel 1)
13
0h
RO_V
X2APIC_EN: Extended Interrupt Mode.
0b: Hardware does not support Extended APIC mode.
1b: Hardware supports Extended APIC mode.
12
0h
RO_V
PDCD:
0: Capable of Dual Channels
1: Not Capable of Dual Channel - only single channel capable.
11:0
0h
RO
Reserved (RSVD): Reserved.