Specification Sheet

Datasheet, Volume 2 of 2 119
Processor Graphics Registers
4.19 Minimum Grant (MINGNT)—Offset 3Eh
The Processor Graphics has no requirement for the settings of Latency Timers.
Access Method
Default: 0h
4.20 Maximum Latency (MAXLAT)—Offset 3Fh
The Processor Graphics has no requirement for the settings of Latency Timers.
Access Method
Default: 0h
Type: CFG
(Size: 8 bits)
Offset: [B:0, D:2, F:0] + 3Eh
7 4 0
0 0 0 0 0 0 0 0
MGV
Bit
Range
Default &
Access
Field Name (ID): Description
7:0
0h
RO
MGV: The Processor Graphics does not burst as a PCI compliant master.
Type: CFG
(Size: 8 bits)
Offset: [B:0, D:2, F:0] + 3Fh
7 4 0
0 0 0 0 0 0 0 0
MLV
Bit
Range
Default &
Access
Field Name (ID): Description
7:0
0h
RO
MLV: The Processor Graphics has no specific requirements for how often it needs to
access the PCI bus.