Specification Sheet

Datasheet, Volume 2 of 2 117
Processor Graphics Registers
4.16 Capabilities Pointer (CAPPOINT)—Offset 34h
This register points to a linked list of capabilities implemented by this device.
Access Method
Default: 40h
4.17 Interrupt Line (INTRLINE)—Offset 3Ch
This 8-bit register is used to communicate interrupt line routing information. It is read/
write and should be implemented by the device. POST software will write the routing
information into this register as it initializes and configures the system.
The value in this register tells which input of the system interrupt controller(s) the
device's interrupt pin is connected to. The device itself does not use this value, rather it
is used by device drivers and operating systems to determine priority and vector
information.
Access Method
Default: 0h
Bit
Range
Default &
Access
Field Name (ID): Description
31:18
0h
RO
RBA: Hardwired to 0's.
17:11
0h
RO
ADMSK: Hardwired to 0s to indicate 256 KB address range.
10:1
0h
RO
Reserved (RSVD): Reserved.
0
0h
RO
RBE: 0: ROM not accessible.
Type: CFG
(Size: 8 bits)
Offset: [B:0, D:2, F:0] + 34h
7 4 0
0 1 0 0 0 0 0 0
CPV
Bit
Range
Default &
Access
Field Name (ID): Description
7:0
40h
RO
CPV: This field contains an offset into the function's PCI Configuration Space for the
first item in the New Capabilities Linked List, the CAPID0 register at offset 40h.
Type: CFG
(Size: 8 bits)
Offset: [B:0, D:2, F:0] + 3Ch