Specification Sheet

10 Datasheet, Volume 2 of 2
12.27 Subsystem ID and Vendor ID Capabilities (SS)—Offset 88h ...................................354
12.28 Subsystem ID and Subsystem Vendor ID (SS)—Offset 8Ch....................................355
12.29 Message Signaled Interrupts Capability ID (MSI)—Offset 90h.................................356
12.30 Message Control (MC)—Offset 92h .....................................................................356
12.31 Message Address (MA)—Offset 94h ....................................................................357
12.32 Message Data (MD)—Offset 98h ........................................................................358
12.33 PCI Express-G Capability List (PEG)—Offset A0h ..................................................358
12.34 PCI Express-G Capabilities (PEG)—Offset A2h ......................................................359
12.35 Device Capabilities (DCAP)—Offset A4h...............................................................359
12.36 Device Control (DCTL)—Offset A8h.....................................................................360
12.37 Device Status (DSTS)—Offset AAh .....................................................................361
12.38 Link Capability (LCAP)—Offset ACh.....................................................................362
12.39 Link Control (LCTL)—Offset B0h.........................................................................364
12.40 Link Status (LSTS)—Offset B2h..........................................................................365
12.41 Slot Capabilities (SLOTCAP)—Offset B4h .............................................................367
12.42 Slot Control (SLOTCTL)—Offset B8h ...................................................................368
12.43 Slot Status (SLOTSTS)—Offset BAh ....................................................................370
12.44 Root Control (RCTL)—Offset BCh........................................................................372
12.45 Root Status (RSTS)—Offset C0h ........................................................................373
12.46 Device Capabilities 2 (DCAP2)—Offset C4h ..........................................................373
12.47 Device Control 2 (DCTL2)—Offset C8h ................................................................375
12.48 Link Control 2 (LCTL2)—Offset D0h ....................................................................376
12.49 Link Status 2 (LSTS2)—Offset D2h .....................................................................378
12.50 Port VC Capability Register 1 (PVCCAP1)—Offset 104h ..........................................379
12.51 Port VC Capability Register 2 (PVCCAP2)—Offset 108h ..........................................380
12.52 Port VC Control (PVCCTL)—Offset 10Ch ..............................................................381
12.53 VC0 Resource Capability (VC0RCAP)—Offset 110h................................................381
12.54 VC0 Resource Control (VC0RCTL)—Offset 114h....................................................382
12.55 VC0 Resource Status (VC0RSTS)—Offset 11Ah ....................................................383
12.56 PEG Uncorrectable Error Status—Offset 1C4h ......................................................384
12.57 PEG Uncorrectable Error Mask—Offset 1C8h ........................................................385
12.58 PEG Uncorrectable Error Severity—Offset 1CCh....................................................386
12.59 PEG Correctable Error Status—Offset 1D0h .........................................................386
12.60 PEG Correctable Error Mask—Offset 1D4h ...........................................................387
12.61 PEG Advanced Error Capabilities and Control—Offset 1D8h ....................................388
12.62 PEG Header Log—Offset 1DCh, 1E0h, 1E4h, 1E8h ................................................388
12.63 PEG Root Error Command—Offset 1ECh ..............................................................389
12.64 PEG Root Error Status—Offset 1F0h....................................................................389
12.65 PEG Error Source Identification—Offset 1F4h .......................................................390
13 PCI Express* Controller (x8) Registers ..................................................................391
13.1 Vendor Identification (VID)—Offset 0h ................................................................393
13.2 Device Identification (DID)—Offset 2h ................................................................393
13.3 PCI Command (PCICMD)—Offset 4h ...................................................................394
13.4 PCI Status (PCISTS)—Offset 6h .........................................................................395
13.5 Revision Identification (RID)—Offset 8h ..............................................................397
13.6 Class Code (CC)—Offset 9h ...............................................................................397
13.7 Cache Line Size (CL)—Offset Ch.........................................................................398
13.8 Header Type (HDR)—Offset Eh ..........................................................................398
13.9 Primary Bus Number (PBUSN)—Offset 18h ..........................................................399
13.10 Secondary Bus Number (SBUSN)—Offset 19h ......................................................399
13.11 Subordinate Bus Number (SUBUSN)—Offset 1Ah..................................................400
13.12 I/O Base Address (IOBASE)—Offset 1Ch .............................................................400
13.13 I/O Limit Address (IOLIMIT)—Offset 1Dh ............................................................401
13.14 Secondary Status (SSTS)—Offset 1Eh ................................................................402