Specification Sheet

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Order Number: 335196-002

7th Generation Intel

Processor

Families for S Platforms and Intel

Core™ X-Series Processor Family

Datasheet, Volume 2 of 2

Supporting 7th Generation Intel

Core™ Processor Families, Intel

Pentium

Processor Family, and Intel

Celeron

Processor Family for

S Platforms and Intel

Core™ X-Series Processor Platforms

May 2017

Summary of content (520 pages)

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7th Generation Intel® Processor Families for S Platforms and Intel® Core™ X-Series Processor Family Datasheet, Volume 2 of 2 Supporting 7th Generation Intel® Core™ Processor Families, Intel® Pentium® Processor Family, and Intel® Celeron® Processor Family for S Platforms and Intel® Core™ X-Series Processor Platforms May 2017 Order Number: 335196-002
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You may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning Intel products described herein. You agree to grant Intel a non-exclusive, royalty-free license to any patent claim thereafter drafted which includes subject matter disclosed herein. No license (express or implied, by estoppel or otherwise) to any intellectual property rights is granted by this document. No computer system can be absolutely secure.
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Contents 1 Introduction ............................................................................................................ 16 2 Processor Configuration Register Definitions and Address Ranges........................... 17 2.1 Register Terminology ......................................................................................... 17 2.2 PCI Devices and Functions .................................................................................. 18 2.3 System Address Map ....................
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3 Host 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 3.20 3.21 3.22 3.23 3.24 3.25 3.26 3.27 3.28 3.29 3.30 3.31 3.32 3.33 3.34 3.35 3.36 3.37 3.38 3.39 3.40 3.41 Bridge/DRAM Registers .................................................................................. Vendor Identification (VID)—Offset 0h ................................................................. Device Identification (DID)—Offset 2h ............................................................
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4.11 4.12 4.13 4.14 4.15 4.16 4.17 4.18 4.19 4.20 4.21 4.22 4.23 4.24 4.25 4.26 4.27 4.28 4.29 4.30 4.31 4.32 4.33 Graphics Memory Range Address (GMADR)—Offset 18h.......................................... 97 I/O Base Address (IOBAR)—Offset 20h................................................................. 98 Subsystem Vendor Identification (SVID2)—Offset 2Ch............................................ 99 Subsystem Identification (SID2)—Offset 2Eh.......................................................
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.27 6.28 6.29 6.30 DMI DMI DMI DMI Uncorrectable Error Mask (DMIUEMSK)—Offset 1C8h .....................................148 Uncorrectable Error Severity (DMIUESEV)—Offset 1CCh .................................149 Correctable Error Status (DMICESTS)—Offset 1D0h .......................................150 Correctable Error Mask (DMICEMSK)—Offset 1D4h ........................................151 7 MCHBAR Registers ..............................................................................................
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.50 7.51 7.52 7.53 7.54 7.55 7.56 7.57 7.58 7.59 7.60 7.61 7.62 7.63 7.64 7.65 7.66 7.67 7.68 7.69 7.70 7.71 7.72 7.73 7.74 7.75 7.76 7.77 7.78 7.79 7.80 7.81 7.82 7.83 7.84 7.85 7.86 7.87 7.88 7.89 7.90 8 PKG—Offset 5848h .......................................................................................... 201 PKG—Offset 5858h .......................................................................................... 201 DDR—Offset 5880h................................................................
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.13 8.14 8.15 8.16 8.17 8.18 8.19 8.20 8.21 8.22 8.23 8.24 8.25 8.26 8.27 8.28 8.29 8.30 8.31 8.32 8.33 Advanced Fault Log Register (AFLOG)—Offset 58h................................................254 Protected Memory Enable Register (PMEN)—Offset 64h .........................................255 Protected Low-Memory Base Register (PLMBASE)—Offset 68h................................256 Protected Low-Memory Limit Register (PLMLIMIT)—Offset 6Ch...............................
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10.31 IOTLB Invalidate Register (IOTLB)—Offset 508h .................................................. 312 11 IMGU Registers ..................................................................................................... 315 11.1 Vendor Identification (VID)—Offset 0h ............................................................... 316 11.2 Device Identification (DID)—Offset 2h ................................................................ 316 11.3 PCI Command (PCICMD)—Offset 4h......................
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12.27 12.28 12.29 12.30 12.31 12.32 12.33 12.34 12.35 12.36 12.37 12.38 12.39 12.40 12.41 12.42 12.43 12.44 12.45 12.46 12.47 12.48 12.49 12.50 12.51 12.52 12.53 12.54 12.55 12.56 12.57 12.58 12.59 12.60 12.61 12.62 12.63 12.64 12.65 13 10 Subsystem ID and Vendor ID Capabilities (SS)—Offset 88h ...................................354 Subsystem ID and Subsystem Vendor ID (SS)—Offset 8Ch....................................355 Message Signaled Interrupts Capability ID (MSI)—Offset 90h.........................
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13.15 13.16 13.17 13.18 13.19 13.20 13.21 13.22 13.23 13.24 13.25 13.26 13.27 13.28 13.29 13.30 13.31 13.32 13.33 13.34 13.35 13.36 13.37 13.38 13.39 13.40 13.41 13.42 13.43 13.44 13.45 13.46 13.47 13.48 13.49 13.50 13.51 13.52 13.53 13.54 13.55 13.56 13.57 13.58 13.59 13.60 13.61 13.62 13.63 13.64 13.65 14 Memory Base Address (MBASE)—Offset 20h ....................................................... 403 Memory Limit Address (MLIMIT)—Offset 22h .......................................................
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14.3 14.4 14.5 14.6 14.7 14.8 14.9 14.10 14.11 14.12 14.13 14.14 14.15 14.16 14.17 14.18 14.19 14.20 14.21 14.22 14.23 14.24 14.25 14.26 14.27 14.28 14.29 14.30 14.31 14.32 14.33 14.34 14.35 14.36 14.37 14.38 14.39 14.40 14.41 14.42 14.43 14.44 14.45 14.46 14.47 14.48 14.49 14.50 14.51 14.52 14.53 14.54 14.55 14.56 14.57 12 PCI Command (PCICMD)—Offset 4h ...................................................................452 PCI Status (PCISTS)—Offset 6h ....................................................
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14.58 14.59 14.60 14.61 14.62 14.63 14.64 14.65 15 PEG PEG PEG PEG PEG PEG PEG PEG Uncorrectable Error Severity—Offset 1CCh ................................................... 502 Correctable Error Status—Offset 1D0h ......................................................... 503 Correctable Error Mask—Offset 1D4h ........................................................... 504 Advanced Error Capabilities and Control—Offset 1D8h....................................
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Figures 2-1 2-2 2-3 2-4 2-5 2-6 2-7 Conceptual Platform PCI Configuration Diagram ......................................................... System Address Range Example .............................................................................. DOS Legacy Address Range .................................................................................... PAM Region Space ................................................................................................. Main Memory Address Range.............
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Revision History Revision Number 001 002 Description • Initial release • • • Added Intel Core X-Series Processor Updated Table 2-3, “S/X Processor PCI Devices and Functions” Updated PCIe Register Chapters — Chapter 12, PCI Express* Controller (X16) Registers. Added registers at Sections 12.56 12.65 — Chapter 13, PCI Express* Controller (X8) Registers. Added registers at Sections 13.56 13.65 — Chapter 14, PCI Express* Controller (X4) Registers. Added registers at Sections 14.56 14.
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Introduction 1 Introduction This is Volume 2 of the 7th Generation Intel® Processor Families for S Platforms and Intel® Core™ X-Series Processor Family Datasheet. Volume 2 provides register information for the processor.
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Processor Configuration Register Definitions and Address Ranges 2 Processor Configuration Register Definitions and Address Ranges This chapter describes the processor configuration register, I/O, and memory address ranges. The chapter provides register terminology. PCI Devices and Functions are described. Note: Processor Graphics does not apply to X-Series processor. 2.
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Processor Configuration Register Definitions and Address Ranges Table 2-2. Register Attribute Modifiers Attribute Modifier Applicable Attribute RO (w/ -V) S RW RW1C Description Sticky: These bits are only re-initialized to their default value by a "Power Good Reset". Note: Does not apply to RO (constant) bits.
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Processor Configuration Register Definitions and Address Ranges Table 2-3.
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Processor Configuration Register Definitions and Address Ranges Figure 2-1. Conceptual Platform PCI Configuration Diagram Note: Processor Graphics does not apply to X-Series processor. 2.3 System Address Map The processor supports 512 GB (39 bits) of addressable memory space and 64 KB+3 of addressable I/O space. This section focuses on how the memory space is partitioned and how the separate memory regions are used.
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Processor Configuration Register Definitions and Address Ranges When running in Processor Graphics mode, processor initiated TileX/Tiley/linear reads/ writes to GMADR range are supported. Write accesses to GMADR linear regions are supported from both DMI and PEG. GMADR write accesses to TileX and TileY regions (defined using fence registers) are not supported from the DMI or the PEG port. GMADR read accesses are not supported from either DMI or PEG.
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Processor Configuration Register Definitions and Address Ranges 3. In the case of overlapping ranges with memory, the memory decode will be given priority. This is an Intel® Trusted Execution Technology (Intel® TXT) requirement. It is necessary to get Intel TXT protection checks, avoiding potential attacks. 4. There are NO Hardware Interlocks to prevent problems in the case of overlapping ranges. 5. Accesses to overlapped ranges may produce indeterminate results. 6.
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Processor Configuration Register Definitions and Address Ranges 2.4 Legacy Address Range The memory address range from 0 to 1 MB is known as Legacy Address.
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Processor Configuration Register Definitions and Address Ranges 2.4.1 DOS Range (0h – 9_FFFFh) The DOS area is 640 KB (0000_0000h – 0009_FFFFh) in size and is always mapped to the main memory. 2.4.2 Legacy Video Area / Compatible SMRAM Area (A_0000h – B_FFFFh) The same address region is used for both Legacy Video Area and Compatible SMRAM.
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Processor Configuration Register Definitions and Address Ranges Figure 2-4. PAM Region Space The PAM registers are mapped in Device 0 configuration space. • ISA Expansion Area (C_0000h – D_FFFFh) • Extended System BIOS Area (E_0000h – E_FFFFh) • System BIOS Area (F_0000h – F_FFFFh) The processor decodes the Core request, then routes to the appropriate destination (DRAM or DMI). Snooped accesses from PCI Express or DMI to this region are snooped on processor Caches.
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Processor Configuration Register Definitions and Address Ranges 2.5 Main Memory Address Range (1 MB – TOLUD) This address range extends from 1 MB to the top of Low Usable physical memory that is permitted to be accessible by the processor (as programmed in the TOLUD register). The processor will route all addresses within this range to the DRAM unless it falls into the optional TSEG, optional ISA Hole, or optional Processor Graphics stolen VGA memory.
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Processor Configuration Register Definitions and Address Ranges 2.5.1 ISA Hole (15 MB –16 MB) The ISA Hole (starting at address F0_0000h) is enabled in the Legacy Access Control Register in Device 0 configuration space. If no hole is created, the processor will route the request to DRAM. If a hole is created, the processor will route the request to DMI, since the request does not target DRAM. These downstream requests will be sent to DMI (subtractive decoding).
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Processor Configuration Register Definitions and Address Ranges To optimally support platform configurations supporting varying amounts of main memory, the protected memory region is defined as two non-overlapping regions: • Protected Low-memory Region: This is defined as the protected memory region below 4 GB to hold the MVMM code/private data, and the initial DMA-remapping structures that control DMA to host physical addresses below 4 GB.
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Processor Configuration Register Definitions and Address Ranges 2.6 PCI Memory Address Range (TOLUD – 4 GB) Top of Low Usable DRAM (TOLUD) – TOLUD is restricted to 4 GB memory (A[31:20]), but the System Agent may support up to a much higher capacity, which is limited by DRAM pins. This address range from the top of low usable DRAM (TOLUD) to 4 GB is normally mapped to the DMI Interface. Device 0 exceptions are: 1. Addresses decoded to the egress port registers (PXPEPBAR) 2.
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Processor Configuration Register Definitions and Address Ranges Figure 2-6.
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Processor Configuration Register Definitions and Address Ranges 2.6.1 APIC Configuration Space (FEC0_0000h – FECF_FFFFh) This range is reserved for APIC configuration space. The I/O APIC(s) usually reside in the PCH portion of the chipset, but may also exist as stand-alone components like PXH. The IOAPIC spaces are used to communicate with IOAPIC interrupt controllers that may be populated in the system.
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Processor Configuration Register Definitions and Address Ranges 2.7 Main Memory Address Space (4 GB to TOUUD) The maximum main memory size supported is 32 GB total DRAM memory. A hole between TOLUD and 4 GB occurs when main memory size approaches 4 GB or larger. As a result, TOM and TOUUD registers and REMAPBASE/REMAPLIMIT registers become relevant. The remap configuration registers exist to remap lost main memory space. The greater than 32-bit remap handling will be handled similar to other MCHs.
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Processor Configuration Register Definitions and Address Ranges 2.7.5 Memory Re-claim Background The following are examples of Memory Mapped IO devices that are typically located below 4 GB: • High BIOS • TSEG • GFX stolen • GTT stolen • XAPIC • Local APIC • MSI Interrupts • Mbase/Mlimit • Pmbase/PMlimit • Memory Mapped IO space that supports only 32B addressing The processor provides the capability to re-claim the physical memory overlapped by the Memory Mapped IO logical address space.
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Processor Configuration Register Definitions and Address Ranges 2.7.7 Memory Remapping An incoming address (referred to as a logical address) is checked to see if it falls in the memory re-map window. The bottom of the re-map window is defined by the value in the REMAPBASE register. The top of the re-map window is defined by the value in the REMAPLIMIT register. An address that falls within this window is re-mapped to the physical memory starting at the address defined by the TOLUD register.
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Processor Configuration Register Definitions and Address Ranges 2.9.1 IOBAR Mapped Access to Device 2 MMIO Space Device 2, Processor Graphics, contains an IOBAR register. If Device 2 is enabled, Processor Graphics registers or the GTT table can be accessed using this IOBAR. The IOBAR is composed of an index register and a data register. MMIO_Index: MMIO_INDEX is a 32-bit register.
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Processor Configuration Register Definitions and Address Ranges 2.11 SMM and VGA Access Through GTT TLB Accesses through GTT TLB address translation SMM DRAM space are not allowed. Writes will be routed to memory address 000C_0000h with byte enables de-asserted and reads will be routed to Memory address 000C_0000h. If a GTT TLB translated address hits SMM DRAM space, an error is recorded.
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Processor Configuration Register Definitions and Address Ranges A set of I/O accesses are consumed by the Processor Graphics device if it is enabled. The mechanisms for Processor Graphics I/O decode and the associated control is explained in following sub-sections. The I/O accesses are forwarded normally to the DMI Interface bus unless they fall within the PCI Express I/O address range as defined by the mechanisms explained below. I/O writes are NOT posted. Memory writes to PCH or PCI Express are posted.
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Processor Configuration Register Definitions and Address Ranges 2.14 Direct Media Interface (DMI) Interface Decode Rules All "SNOOP semantic" PCI Express* transactions are kept coherent with processor caches. All "Snoop not required semantic" cycles reference the main DRAM address range. PCI Express non-snoop initiated cycles are not snooped.
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Processor Configuration Register Definitions and Address Ranges 2.14.2 Traffic Class (TC) / Virtual Channel (VC) Mapping Details • VC0 (enabled by default) — Snoop port and Non-snoop Asynchronous transactions are supported. — Internal Graphics GMADR writes can occur. These writes will NOT be snooped regardless of the snoop not required (SNR) bit. — Processor Graphics GMADR reads (unsupported). — Peer writes can occur. The SNR bit is ignored. — MSI can occur.
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Processor Configuration Register Definitions and Address Ranges Figure 2-7.
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Processor Configuration Register Definitions and Address Ranges 2.15 PCI Express* Interface Decode Rules All "SNOOP semantic" PCI Express* transactions are kept coherent with processor caches. All "Snoop not required semantic" cycles should reference the direct DRAM address range. PCI Express non-snoop initiated cycles are not snooped.
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Processor Configuration Register Definitions and Address Ranges • Processor Graphics VGA in Device 0 Function 0 is enabled through register GGC bit 1. • Processor Graphics's memory accesses (PCICMD2 04h – 05h, MAE bit 1) in Device 2 configuration space are enabled. • VGA compatibility memory accesses (VGA Miscellaneous Output register – MSR Register, bit 1) are enabled. • Software sets the proper value for VGA Memory Map Mode register (VGA GR06 Register, bits 3:2). See the following table for translations.
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Processor Configuration Register Definitions and Address Ranges Note: Additional qualification within Processor Graphics comprehends internal MDA support. The VGA and MDA enabling bits detailed below control ranges not mapped to Processor Graphics.
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Processor Configuration Register Definitions and Address Ranges The same registers control mapping of VGA I/O address ranges. The VGA I/O range is defined as addresses where A[9:0] are in the ranges 3B0h to 3BBh and 3C0h to 3DFh (inclusive of ISA address aliases – A[15:10] are not decoded). The function and interaction of these two bits is described below.
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Processor Configuration Register Definitions and Address Ranges 2.17 I/O Mapped Registers The processor contains two registers that reside in the processor I/O address space the Configuration Address (CONFIG_ADDRESS) Register and the Configuration Data (CONFIG_DATA) Register. The Configuration Address Register enables/disables the configuration space and determines what portion of configuration space is visible through the Configuration Data window.
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Host Bridge/DRAM Registers 3 Host Bridge/DRAM Registers Table 3-1.
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Host Bridge/DRAM Registers Table 3-1. Summary of Bus: 0, Device: 0, Function: 0 (CFG) (Continued) Size (Bytes) Offset Register Name (Register Symbol) Default Value B8–BBh 4 TSEG Memory Base (TSEGMB)—Offset B8h 0h BC–BFh 4 Top of Low Usable DRAM (TOLUD)—Offset BCh 100000h DC–DFh 4 Scratchpad Data (SKPD)—Offset DCh 0h E4–E7h 4 Capabilities A (CAPID0)—Offset E4h 0h E8–EBh 4 Capabilities B (CAPID0)—Offset E8h 0h EC–EFh 4 Capabilities C (CAPID0)—Offset ECh 0h 3.
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Host Bridge/DRAM Registers 3.2 Device Identification (DID)—Offset 2h This register combined with the Vendor Identification register uniquely identifies any PCI device. Access Method Type: CFG (Size: 16 bits) Offset: [B:0, D:0, F:0] + 2h Default: 59XXh 15 1 0 8 1 1 0 0 1 4 X X X Bit Range 3.
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Host Bridge/DRAM Registers 3.4 Bit Range Default & Access 15:10 0h RO Reserved (RSVD): Reserved. 9 0h RO FB2B: Fast Back-to-Back Enable: This bit controls whether or not the master can do fast back-to-back write. Since device 0 is strictly a target this bit is not implemented and is hardwired to 0. Writes to this bit position have no effect. 8 0h RW SERRE: SERR Enable: This bit is a global enable bit for Device 0 SERR messaging.
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Host Bridge/DRAM Registers 0 0 1 CLIST 0 0 0 0 0 RSVD 1 MC66 4 0 RSVD 0 FB2B STAS Default & Access 0 DPD 0 DEVT 0 RTAS SSE 8 0 RMAS 0 Bit Range 62 12 0 DPE 15 Field Name (ID): Description 15 0h RW1C DPE: Detected Parity Error: This bit is set when this Device receives a Poisoned TLP. 14 0h RW1C SSE: Signaled System Error: This bit is set to 1 when Device 0 generates an SERR message over DMI for any enabled Device 0 error condition.
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Host Bridge/DRAM Registers 3.5 Revision Identification (RID)—Offset 8h This register contains the revision number of Device #0. These bits are read only and writes to this register have no effect. Access Method Type: CFG (Size: 8 bits) Offset: [B:0, D:0, F:0] + 8h Default: 0h 7 4 0 0 0 0 0 0 Bit Range 3.
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Host Bridge/DRAM Registers 3.7 Bit Range Default & Access 23:16 6h RO BCC: Base Class Code: This is an 8-bit value that indicates the base class code for the Host Bridge device. This code has the value 06h, indicating a Bridge device. 15:8 0h RO SUBCC: Sub-Class Code: This is an 8-bit value that indicates the category of Bridge into which the Host Bridge device falls. The code is 00h indicating a Host Bridge.
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Host Bridge/DRAM Registers 3.8 Subsystem Vendor Identification (SVID)—Offset 2Ch This value is used to identify the vendor of the subsystem. Access Method Type: CFG (Size: 16 bits) Offset: [B:0, D:0, F:0] + 2Ch Default: 0h 15 12 0 0 0 8 0 0 0 4 0 0 0 0 0 0 0 0 0 0 SUBVID 0 Bit Range Default & Access 0h RW_O 15:0 3.9 Field Name (ID): Description SUBVID: Subsystem Vendor ID: This field should be programmed during boot-up to indicate the vendor of the system board.
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Host Bridge/DRAM Registers 3.10 Capabilities Pointer (CAPPTR)—Offset 34h The CAPPTR provides the offset that is the pointer to the location of the first device capability in the capability list. Access Method Type: CFG (Size: 8 bits) Offset: [B:0, D:0, F:0] + 34h Default: E0h 7 4 1 1 0 0 0 0 0 CAPPTR 1 0 Bit Range 7:0 3.11 Default & Access Field Name (ID): Description CAPPTR: Capabilities Pointer: Pointer to the offset of the first capability ID register block.
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Host Bridge/DRAM Registers 3.12 Bit Range Default & Access 63:39 0h RO Reserved (RSVD): Reserved. 38:12 0h RW PXPEPBAR: This field corresponds to bits 38 to 12 of the base address PCI Express Egress Port MMIO configuration space. BIOS will program this register resulting in a base address for a 4KB block of contiguous memory address space. This register ensures that a naturally aligned 4KB space is allocated within the first 512GB of addressable memory space.
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Host Bridge/DRAM Registers 3.13 Bit Range Default & Access 63:39 0h RO Reserved (RSVD): Reserved. 38:15 0h RW MCHBAR: This field corresponds to bits 38 to 15 of the base address Host Memory Mapped configuration space. BIOS will program this register resulting in a base address for a 32KB block of contiguous memory address space. This register ensures that a naturally aligned 32KB space is allocated within the first 512GB of addressable memory space.
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Host Bridge/DRAM Registers Bit Range Field Name (ID): Description 0h RO 5:3 Reserved (RSVD): Reserved. 0h RW_L VAMEN: Enables the use of the iGFX engines for Versatile Acceleration. 1: iGFX engines are in Versatile Acceleration Mode. Device 2 Class Code is 048000h. 0:- iGFX engines are in iGFX Mode. Device 2 Class Code is 030000h. 1 0h RW_L IVD: 0: Enable. Device 2 (Processor Graphics) claims VGA memory and IO cycles, the SubClass Code within Device 2 Class Code register is 00. 1: Disable.
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Host Bridge/DRAM Registers Bit Range Default & Access 31:16 0h RO Reserved (RSVD): Reserved. 1h RW_L D8EN: 0: Bus 0 Device 8 is disabled and not visible. 1: Bus 0 Device 8 is enabled and visible. This bit will be set to 0b and remain 0b if Device 8 capability is disabled. 14 0h RW D7EN: 0: Bus 0 Device 7 is disabled and not visible. 1: Bus 0 Device 7 is enabled and visible. Non-production BIOS code should provide a setup option to enable Bus 0 Device 7.
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Host Bridge/DRAM Registers Bit Range Field Name (ID): Description 1h RW_L D1F1EN: 0: Bus 0 Device 1 Function 1 is disabled and hidden. 1: Bus 0 Device 1 Function 1 is enabled and visible. This bit will be set to 0b and remain 0b if: - PEG11 capability is disabled by fuses, OR - PEG11 is disabled by strap (PEG0CFGSEL) 1 1h RW_L D1F2EN: 0: Bus 0 Device 1 Function 2 is disabled and hidden. 1: Bus 0 Device 1 Function 2 is enabled and visible.
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Host Bridge/DRAM Registers Bit Range Field Name (ID): Description 5 0h RW_L 4 0h RW_L OVTATTACK: Override of Unsolicited Connection State Attack and Terminate. 0: Disable Override. Attack Terminate allowed. 1: Enable Override. Attack Terminate disallowed. This register bit is locked when PAVPE is set. 3 0h RW_L HVYMODSEL: This bit is applicable only for PAVP2 operation mode.
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Host Bridge/DRAM Registers 3.16 DMA Protected Range (DPR)—Offset 5Ch DMA protected range register. Access Method Type: CFG (Size: 32 bits) Offset: [B:0, D:0, F:0] + 5Ch Default: 0h 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 LOCK 0 8 PRS 0 1 2 EPM 0 1 6 RSVD 0 2 0 DPRSIZE 0 2 4 TopOfDPR 0 2 8 RSVD 3 1 Bit Range Default & Access 31:20 0h ROV TopOfDPR: Top address + 1 of DPR. This is the base of TSEG.
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Host Bridge/DRAM Registers 3.17 PCI Express Register Range Base Address (PCIEXBAR)—Offset 60h This is the base address for the PCI Express configuration space. This window of addresses contains the 4KB of configuration space for each PCI Express device that can potentially be part of the PCI Express Hierarchy associated with the Uncore. There is no actual physical memory within this window of up to 256MB that can be addressed. The actual size of this range is determined by a field in this register.
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Host Bridge/DRAM Registers Bit Range Default & Access 63:39 0h RO Reserved (RSVD): Reserved. 0h RW PCIEXBAR: This field corresponds to bits 38 to 28 of the base address for PCI Express enhanced configuration space. BIOS will program this register resulting in a base address for a contiguous memory address space. The size of the range is defined by bits [2:1] of this register.
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Host Bridge/DRAM Registers compliant memory mapped space. On reset, the Root Complex configuration space is disabled and should be enabled by writing a 1 to DMIBAREN [Dev 0, offset 68h, bit 0] All the bits in this register are locked in Intel TXT mode. Access Method Type: CFG (Size: 64 bits) Offset: [B:0, D:0, F:0] + 68h Default: 0h 6 3 6 0 5 6 5 2 4 8 4 4 4 0 3 6 3 2 2 8 2 4 2 0 1 6 1 2 8 4 0 3.
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Host Bridge/DRAM Registers Access Method Type: CFG (Size: 64 bits) Offset: [B:0, D:0, F:0] + 70h Default: 7FFFF00000h 6 3 6 0 5 6 5 2 4 8 4 4 4 0 3 6 3 2 2 8 2 4 2 0 1 6 1 2 8 4 0 Bit Range Default & Access 63:39 0h RO Reserved (RSVD): Reserved. 38:20 7FFFFh RW_L MEBASE: Corresponds to A[38:20] of the base address memory range that is allocated to the ME. 0h RO Reserved (RSVD): Reserved. 19:0 3.
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Host Bridge/DRAM Registers 6 3 6 0 5 6 5 2 4 8 4 4 4 0 3 6 3 2 2 8 2 4 2 0 1 6 1 2 8 4 0 3.21 Bit Range Default & Access 63:39 0h RO RSVD ME_STLEN_EN MELCK RSVD RSVD MEMASK 0000000000000000000000000000000000000000000000000000000000000000 Field Name (ID): Description Reserved (RSVD): Reserved. 38:20 0h RW_L MEMASK: This field indicates the bits that should match MEBASE in order to qualify as an ME Memory Range access.
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Host Bridge/DRAM Registers The RE and WE attributes permit a memory segment to be Read Only, Write Only, Read/Write or Disabled. For example, if a memory segment has RE=1 and WE=0, the segment is Read Only. Access Method Type: CFG (Size: 8 bits) Offset: [B:0, D:0, F:0] + 80h Default: 0h 4 Bit Range 0 0 0 RSVD 0 0 Field Name (ID): Description 0h RO Reserved (RSVD): Reserved.
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Host Bridge/DRAM Registers The RE and WE attributes permit a memory segment to be Read Only, Write Only, Read/Write or Disabled. For example, if a memory segment has RE=1 and WE=0, the segment is Read Only. Access Method Type: CFG (Size: 8 bits) Offset: [B:0, D:0, F:0] + 81h Default: 0h 4 Bit Range 0 0 RSVD 0 0 0 Field Name (ID): Description 0h RO Reserved (RSVD): Reserved.
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Host Bridge/DRAM Registers WE - Write Enable. When WE=1, the host write accesses to the corresponding memory segment are claimed by the Uncore and directed to main memory. Conversely, when WE=0, the host read accesses are directed to DMI. The RE and WE attributes permit a memory segment to be Read Only, Write Only, Read/Write or Disabled. For example, if a memory segment has RE=1 and WE=0, the segment is Read Only.
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Host Bridge/DRAM Registers RE - Read Enable. When RE=1, the host read accesses to the corresponding memory segment are claimed by the Uncore and directed to main memory. Conversely, when RE=0, the host read accesses are directed to DMI. WE - Write Enable. When WE=1, the host write accesses to the corresponding memory segment are claimed by the Uncore and directed to main memory. Conversely, when WE=0, the host read accesses are directed to DMI.
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Host Bridge/DRAM Registers Two bits are used to specify memory attributes for each memory segment. These bits apply to host accesses to the PAM areas. These attributes are: RE - Read Enable. When RE=1, the host read accesses to the corresponding memory segment are claimed by the Uncore and directed to main memory. Conversely, when RE=0, the host read accesses are directed to DMI. WE - Write Enable.
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Host Bridge/DRAM Registers 3.26 Programmable Attribute Map 5 (PAM5)—Offset 85h This register controls the read, write and shadowing attributes of the BIOS range from E_0000h to E_7FFFh. The Uncore allows programmable memory attributes on 13 legacy memory segments of various sizes in the 768KB to 1MB address range. Seven Programmable Attribute Map (PAM) registers are used to support these features. Cacheability of these areas is controlled via the MTRR register in the core.
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Host Bridge/DRAM Registers 3.27 Programmable Attribute Map 6 (PAM6)—Offset 86h This register controls the read, write and shadowing attributes of the BIOS range from E_8000h to E_FFFFh. The Uncore allows programmable memory attributes on 13 legacy memory segments of various sizes in the 768KB to 1MB address range. Seven Programmable Attribute Map (PAM) registers are used to support these features. Cacheability of these areas is controlled via the MTRR register in the core.
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Host Bridge/DRAM Registers 3.28 Legacy Access Control (LAC)—Offset 87h This 8-bit register controls steering of MDA cycles and a fixed DRAM hole from 1516MB. There can only be at most one MDA device in the system. Access Method Type: CFG (Size: 8 bits) Offset: [B:0, D:0, F:0] + 87h Default: 0h 86 0 Default & Access 7 0h RW 6:4 0h RO 0 0 0 0 MDAP10 HEN Bit Range 0 MDAP11 0 RSVD 0 0 MDAP12 4 MDAP60 7 Field Name (ID): Description HEN: This field enables a memory hole in DRAM space.
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Host Bridge/DRAM Registers Bit Range 3 2 Datasheet, Volume 2 of 2 Default & Access Field Name (ID): Description 0h RW MDAP60: This bit works with the VGA Enable bits in the BCTRL register of Device 1 Function 2 to control the routing of Processor initiated transactions targeting MDA compatible I/O and memory address ranges. This bit should not be set if device 1 function 2 VGA Enable bit is not set.
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Host Bridge/DRAM Registers Bit Range 1 0 88 Default & Access Field Name (ID): Description 0h RW MDAP11: This bit works with the VGA Enable bits in the BCTRL register of Device 1 Function 1 to control the routing of Processor initiated transactions targeting MDA compatible I/O and memory address ranges. This bit should not be set if device 1 function 1 VGA Enable bit is not set. If device 1 function 1 VGA enable bit is not set, then accesses to IO address range x3BCh-x3BFh remain on the backbone.
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Host Bridge/DRAM Registers 3.29 System Management RAM Control (SMRAMC)— Offset 88h The SMRAMC register controls how accesses to Compatible SMRAM spaces are treated. The Open, Close and Lock bits function only when G_SMRAME bit is set to 1. Also, the Open bit should be reset before the Lock bit is set.
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Host Bridge/DRAM Registers 3.30 Remap Base Address Register (REMAPBASE)— Offset 90h Access Method Type: CFG (Size: 64 bits) Offset: [B:0, D:0, F:0] + 90h Default: 7FFFF00000h 6 3 6 0 5 6 5 2 4 8 4 4 4 0 3 6 3 2 2 8 2 4 2 0 1 6 1 2 8 4 0 Bit Range Default & Access 63:39 0h RO 38:20 19:1 0 90 7FFFFh RW_L LOCK RSVD RSVD REMAPBASE 0000000000000000000000000111111111111111111100000000000000000000 Field Name (ID): Description Reserved (RSVD): Reserved.
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Host Bridge/DRAM Registers 3.31 Remap Limit Address Register (REMAPLIMIT)— Offset 98h Access Method Type: CFG (Size: 64 bits) Offset: [B:0, D:0, F:0] + 98h Default: 0h 6 3 6 0 5 6 5 2 4 8 4 4 4 0 3 6 3 2 2 8 2 4 2 0 1 6 1 2 8 4 0 LOCK RSVD RSVD REMAPLMT 0000000000000000000000000000000000000000000000000000000000000000 Bit Range Default & Access 63:39 0h RO Reserved (RSVD): Reserved. 0h RW_L REMAPLMT: The value in this register defines the upper boundary of the Remap window.
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Host Bridge/DRAM Registers 3.32 Top of Memory (TOM)—Offset A0h This Register contains the size of physical memory. BIOS determines the memory size reported to the OS using this Register. Access Method Type: CFG (Size: 64 bits) Offset: [B:0, D:0, F:0] + A0h Default: 7FFFF00000h 6 3 6 0 5 6 5 2 4 8 4 4 4 0 3 6 3 2 2 8 2 4 2 0 1 6 1 2 8 4 0 LOCK Bit Range Default & Access 63:39 0h RO Reserved (RSVD): Reserved.
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Host Bridge/DRAM Registers 6 3 6 0 5 6 5 2 4 8 4 4 4 0 3 6 3 2 2 8 2 4 2 0 1 6 1 2 8 4 0 Bit Range Default & Access 63:39 0h RO 38:20 19:1 0 3.34 LOCK RSVD RSVD TOUUD 0000000000000000000000000000000000000000000000000000000000000000 Field Name (ID): Description Reserved (RSVD): Reserved. 0h RW_L TOUUD: This register contains bits 38 to 20 of an address one byte above the maximum DRAM memory above 4G that is usable by the operating system.
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Host Bridge/DRAM Registers Bit Range Default & Access 31:20 0h RW_L BDSM: This register contains bits 31 to 20 of the base address of stolen DRAM memory. BIOS determines the base of graphics stolen memory by subtracting the graphics stolen memory size (PCI Device 0 offset 50 bits 15:8) from TOLUD (PCI Device 0 offset BC bits 31:20). 0h RO Reserved (RSVD): Reserved. 0h RW_KL LOCK: This bit will lock all writeable settings in this register, including itself. 19:1 0 3.
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Host Bridge/DRAM Registers 3.36 TSEG Memory Base (TSEGMB)—Offset B8h This register contains the base address of TSEG DRAM memory. BIOS determines the base of TSEG memory which should be at or below Graphics Base of GTT Stolen Memory (PCI Device 0 Offset B4 bits 31:20).
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Host Bridge/DRAM Registers According to the above equation, TOLUD is originally calculated to: 4GB = 1_0000_0000h The system memory requirements are: 4GB (max addressable space) - 1GB (pci space) - 35MB (lost memory) = 3GB - 35MB (minimum granularity) = 0_ECB0_0000h Since 0_ECB0_0000h (PCI and other system requirements) is less than 1_0000_0000h, TOLUD should be programmed to ECBh. These bits are Intel TXT lockable.
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Host Bridge/DRAM Registers 3.38 Scratchpad Data (SKPD)—Offset DCh This register holds 32 writable bits with no functionality behind them. It is for the convenience of BIOS and graphics drivers. Access Method Type: CFG (Size: 32 bits) Offset: [B:0, D:0, F:0] + DCh Default: 0h 3 1 0 0 0 2 4 0 0 0 0 2 0 0 0 0 0 1 6 0 0 0 0 1 2 0 0 0 0 8 0 0 0 0 4 0 0 0 0 0 0 0 0 0 SKPD 0 2 8 Bit Range Default & Access 0h RW 31:0 3.
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Host Bridge/DRAM Registers 3.40 Bit Range Default & Access 31:26 0h RO 25 0h RO 24 0h RO 23 0h RO_KFW Field Name (ID): Description Reserved (RSVD): Reserved. ECCDIS: 0: ECC capable 1: Not ECC capable Reserved (RSVD): Reserved. VTDD: 0: Enable VTd 1: Disable VTd 22:15 0h RO Reserved (RSVD): Reserved. 14 0h RO DDPCD: Allows Dual Channel operation but only supports 1 DIMM per channel. 0: 2 DIMMs per channel enabled 1: 2 DIMMs per channel disabled.
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Host Bridge/DRAM Registers Bit Range 31 Default & Access 0h RO_KFW Field Name (ID): Description IMGU_DIS: 0: Device 5 associated memory spaces are accessible. 1: Device 5 associated memory and IO spaces are disabled by hardwiring the D1F2EN field, bit 1 of the Device Enable register, (DEVEN Dev 0 Offset 54h) to '0'. 30:29 0h RO Reserved (RSVD): Reserved. 28 0h RO SMT: This setting indicates whether or not the Processor is SMT capable.
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Host Bridge/DRAM Registers Bit Range 3.41 Default & Access Field Name (ID): Description DMFC_DDR3: This field controls which values may be written to the Memory Frequency Select field 6:4 of the Clocking Configuration registers (MCHBAR Offset C00h). Any attempt to write an unsupported value will be ignored.
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Processor Graphics Registers 4 Processor Graphics Registers Table 4-1.
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Processor Graphics Registers 4.1 Vendor Identification (VID2)—Offset 0h This register combined with the Device Identification register uniquely identifies any PCI device. Access Method Type: CFG (Size: 16 bits) Offset: [B:0, D:2, F:0] + 0h Default: 8086h 15 0 0 8 0 0 0 0 4 0 1 0 0 0 0 0 1 1 0 VID 1 12 Bit Range Default & Access 8086h RO 15:0 4.2 Field Name (ID): Description VID: PCI standard identification for Intel.
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Processor Graphics Registers 4.3 PCI Command (PCICMD)—Offset 4h This 16-bit register provides basic control over the Processor Graphics's ability to respond to PCI cycles. The PCICMD Register in the Processor Graphics disables the Processor Graphics PCI compliant master accesses to main memory.
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Processor Graphics Registers Bit Range 4.4 Default & Access Field Name (ID): Description 2 0h RW BME: 0: Disable Processor Graphics bus mastering. 1: Enable the Processor Graphics to function as a PCI compliant master. 1 0h RW MAE: This bit controls the Processor Graphics's response to memory space accesses. 0: Disable. 1: Enable. 0 0h RW IOAE: This bit controls the Processor Graphics's response to I/O space accesses. 0: Disable. 1: Enable.
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Processor Graphics Registers Bit Range Field Name (ID): Description 6 0h RO UDF: Hardwired to 0. 5 0h RO C66: N/A - Hardwired to 0. 4 1h RO CLIST: This bit is set to 1 to indicate that the register at 34h provides an offset into the function's PCI Configuration Space containing a pointer to the location of the first item in the list. 3 0h RO_V INTSTS: This bit reflects the state of the interrupt in the device.
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Processor Graphics Registers 4.6 Class Code (CC)—Offset 9h This register contains the device programming interface information related to the SubClass Code and Base Class Code definition for the Processor Graphics. This register also contains the Base Class Code and the function sub-class in relation to the Base Class Code.
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Processor Graphics Registers Bit Range 7:0 4.8 Default & Access 0h RW Field Name (ID): Description CLS: This field is implemented by PCI Express devices as a read-write field for legacy compatibility purposes but has no effect on any PCI Express device behavior. Master Latency Timer (MLT2)—Offset Dh The Processor Graphics does not support the programmability of the master latency timer because it does not perform bursts.
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Processor Graphics Registers Bit Range 4.10 Default & Access Field Name (ID): Description 7 0h RO MFUNC: Indicates if the device is a Multi-Function Device. The Value of this register is hardwired to 0, indicating the processor graphics is a single function. 6:0 0h RO H: This is a 7-bit value that indicates the Header Code for the Processor Graphics. This code has the value 00h, indicating a type 0 configuration space format.
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Processor Graphics Registers Bit Range 4.11 Default & Access Field Name (ID): Description 3 0h RO PREFMEM: Hardwired to 0 to prevent prefetching. 2:1 2h RO MEMTYP: 00: To indicate 32 bit base address 01: Reserved 10: To indicate 64 bit base address 11: Reserved 0 0h RO MIOS: Hardwired to 0 to indicate memory space. Graphics Memory Range Address (GMADR)— Offset 18h GMADR is the PCI aperture used by S/W to access tiled GFX surfaces in a linear fashion.
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Processor Graphics Registers Bit Range Field Name (ID): Description 0h RW_L ADMSK256: This bit is either part of the Memory Base Address (R/W) or part of the Address Mask (RO), depending on the value of MSAC[4:0]. See MSAC (Dev 2, Func 0, offset 62h) for details. 26:4 0h RO ADM: Hardwired to 0s to indicate at least 128MB address range. 3 1h RO 2:1 2h RO MEMTYP: Memory Type (MEMTYP): 00: indicate 32-bit address. 10: Indicate 64-bit address 0 0h RO MIOS: Hardwired to 0 to indicate memory space.
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Processor Graphics Registers 4.13 Bit Range Default & Access 31:16 0h RO Reserved (RSVD): Reserved. 15:6 0h RW IOBASE: Set by the OS, these bits correspond to address signals [15:6]. Note: This field is RO 0s if DEV2CTL[0] IOBARDIS is 1b. 5:3 0h RO Reserved (RSVD): Reserved. 2:1 0h RO MEMTYPE: Hardwired to 0s to indicate 32-bit address. 0 1h RO MIOS: Hardwired to “1” to indicate IO space. Note: This field is RO 0s if DEV2CTL[0] IOBARDIS is 1b.
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Processor Graphics Registers 4.14 Subsystem Identification (SID2)—Offset 2Eh This register is used to uniquely identify the subsystem where the PCI device resides. Access Method Type: CFG (Size: 16 bits) Offset: [B:0, D:2, F:0] + 2Eh Default: 0h 15 12 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 SUBID 0 8 Bit Range Field Name (ID): Description SUBID: This value is used to identify a particular subsystem. This field should be programmed by BIOS during boot-up.
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Processor Graphics Registers 4.16 Bit Range Default & Access 31:18 0h RO RBA: Hardwired to 0's. 17:11 0h RO ADMSK: Hardwired to 0s to indicate 256 KB address range. 10:1 0h RO Reserved (RSVD): Reserved. 0 0h RO RBE: 0: ROM not accessible. Field Name (ID): Description Capabilities Pointer (CAPPOINT)—Offset 34h This register points to a linked list of capabilities implemented by this device.
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Processor Graphics Registers 7 4 0 0 0 0 0 0 0 0 INTCON 0 Bit Range 7:0 4.18 Default & Access Field Name (ID): Description INTCON: Used to communicate interrupt line routing information. POST software writes the routing information into this register as it initializes and configures the system. The value in this register indicates to which input of the system interrupt controller the device's interrupt pin is connected.
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Processor Graphics Registers 4.19 Minimum Grant (MINGNT)—Offset 3Eh The Processor Graphics has no requirement for the settings of Latency Timers. Access Method Type: CFG (Size: 8 bits) Offset: [B:0, D:2, F:0] + 3Eh Default: 0h 7 4 0 0 0 0 0 0 0 MGV 0 0 Bit Range 7:0 4.20 Default & Access 0h RO Field Name (ID): Description MGV: The Processor Graphics does not burst as a PCI compliant master.
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Processor Graphics Registers 4.21 Capabilities A (CAPID0)—Offset 44h Control of bits in this register are only required for customer visible SKU differentiation. Access Method Type: CFG (Size: 32 bits) Offset: [B:0, D:2, F:0] + 44h Default: 0h 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 RSVD 0 PDCD 0 DDPCD 0 8 Bit Range Default & Access 31:26 0h RO Reserved (RSVD): Reserved.
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Processor Graphics Registers 4.22 Capabilities B (CAPID0)—Offset 48h Control of bits in this register are only required for customer visible SKU differentiation.
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Processor Graphics Registers Bit Range Field Name (ID): Description PEGG3_DIS: the processor: PCIe Gen 3 Disable fuse. This fuse will be strap selectable/modifiable to enable SKU capabilities. This is a defeature fuse -- an unprogrammed device should have PCIe Gen 3 capabilities enabled.
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Processor Graphics Registers 4.23 Device Enable (DEVEN0)—Offset 54h Allows for enabling/disabling of PCI devices and functions that are within the Processor package. The table below the bit definitions describes the behavior of all combinations of transactions to devices controlled by this register. All the bits in this register are Intel TXT Lockable.
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Processor Graphics Registers Bit Range Field Name (ID): Description 6 0h RO Reserved (RSVD): Reserved. 5 1h RO_V D3EN: 0: Bus 0 Device 3 is disabled and hidden 1: Bus 0 Device 3 is enabled and visible This bit will be set to 0b and remain 0b if Device 3 capability is disabled. 4 1h RO_V D2EN: 0: Bus 0 Device 2 is disabled and hidden 1: Bus 0 Device 2 is enabled and visible This bit will be set to 0b and remain 0b if Device 2 capability is disabled.
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Processor Graphics Registers Bit Range Default & Access 31:20 0h RO_V BDSM: This register contains bits 31 to 20 of the base address of stolen DRAM memory. BIOS determines the base of graphics stolen memory by subtracting the graphics stolen memory size (PCI Device 0 offset 50 bits 15:8) from TOLUD (PCI Device 0, offset BC, bits 31:20). 0h RO Reserved (RSVD): Reserved. 0h RO_V LOCK: This bit will lock all writeable settings in this register, including itself. 19:1 0 4.
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Processor Graphics Registers Bit Range 3 2 1 0 126 Default & Access Field Name (ID): Description 0h RW_KV APSZ3: This field is used in conjuction with other APSZ* fields to determine the size of Aperture (GMADR) and affects certain bits of GMADR register. The description below is for all APSZ* fields 4:0 00000 = 128MB => GMADR.B[26:4] is hardwired to 0 00001 = 256MB => GMADR.B[27] = 0, RO 00010 = illegal (hardware will treat this as 00011) 00011 = 512MB => GMADR.
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Processor Graphics Registers 4.26 PCI Express Capability Header (PCIECAPHDR)— Offset 70h This is the header register for the PCI Express Capability Structure, allowing the exposure of PCI Express Extended Capabilities which are required for SVM OS support. Access Method Type: CFG (Size: 16 bits) Offset: [B:0, D:2, F:0] + 70h Default: AC10h 15 12 0 1 8 0 1 1 0 0 4 0 0 0 Bit Range 4.
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Processor Graphics Registers Bit Range 4.28 Default & Access Field Name (ID): Description 15:8 D0h RO POINTNEXT: This contains a pointer to the next item in the capabilities list which is the Power Management capability. 7:0 5h RO CAPID: Value of 05h identifies this linked list item (capability structure) as being for MSI registers. Message Control (MC)—Offset AEh Message Signaled Interrupt control register.
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Processor Graphics Registers 4.29 Message Address (MA)—Offset B0h This register contains the Message Address for MSIs sent by the device. Access Method Type: CFG (Size: 32 bits) Offset: [B:0, D:2, F:0] + B0h Default: 0h 2 8 0 0 0 0 0 0 0 2 0 0 0 0 0 1 6 0 0 0 0 1 2 0 0 0 0 4 8 0 0 0 0 0 0 0 0 0 0 0 MESSADD 0 2 4 Bit Range 4.
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Processor Graphics Registers Bit Range Default & Access 4.31 MESSDATA: Base message data pattern assigned by system software and used to handle an MSI from the device. When the device should generate an interrupt request, it writes a 32-bit value to the memory address specified in the MA register. The upper 16 bits are always set to 0. The lower 16 bits are supplied by this register.
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Processor Graphics Registers 4.32 Power Management Capabilities (PMCAP)—Offset D2h This register provides information on the capabilities of the function related to power management. Access Method Type: CFG (Size: 16 bits) Offset: [B:0, D:2, F:0] + D2h Default: 22h 0 4 0 0 0 1 0 0 0 1 0 VER 0 PMECLK 0 RSVD 8 0 DSI 0 RSVD 0 D1 12 0 PMES 0 D2 15 Bit Range Default & Access 15:11 0h RO PMES: This field indicates the power states in which the Processor Graphics may assert PME#.
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Processor Graphics Registers 4.33 Power Management Control/Status (PMCS)— Offset D4h Access Method Type: CFG (Size: 16 bits) Offset: [B:0, D:2, F:0] + D4h Default: 0h Default & Access 8 0 0 0 4 0 0 0 0 0 0 0 0 0 0 PWRSTAT PMESTS Bit Range 0 RSVD 0 PMEEN 12 0 DSCALE 0 DSEL 15 Field Name (ID): Description 15 0h RO PMESTS: This bit is 0 to indicate that Processor Graphics does not support PME# generation from D3 (cold).
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Dynamic Power Performance Management (DPPM) Registers 5 Dynamic Power Performance Management (DPPM) Registers Table 5-1. Summary of Bus: 0, Device: 4, Function: 0 (CFG) Size (Bytes) Offset Default Value Register Name (Register Symbol) 54–57h 4 Device Enable (DEVEN)—Offset 54h 84BFh E4–E7h 4 Capabilities A (CAPID0)—Offset E4h 0h E8–EBh 4 Capabilities B (CAPID0)—Offset E8h 0h 5.
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Dynamic Power Performance Management (DPPM) Registers Bit Range 13 12:11 Field Name (ID): Description 0h RO_V D6EN: Reserved (RSVD): 0h RO Reserved (RSVD): Reserved. 10 1h RO_V 9:8 0h RO D5EN: 0: Bus 0 Device 5 is disabled and not visible. 1: Bus 0 Device 5 is enabled and visible. This bit will be set to 0b and remain 0b if Device 5 capability is disabled. Reserved (RSVD): Reserved. D4EN: 0: Bus 0 Device 4 is disabled and not visible. 1: Bus 0 Device 4 is enabled and visible.
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Dynamic Power Performance Management (DPPM) Registers Bit Range Default & Access 31:26 0h RO 25 0h RO_V 24 0h RO 23 0h RO_V 22:15 0h RO 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 4 0 0 0 0 0 0 0 0 0 RSVD 0 PDCD 0 ECCDIS 0 DDPCD 0 1 2 X2APIC_EN 0 1 6 RSVD 0 2 0 RSVD 0 2 4 RSVD 0 2 8 VTDD 3 1 Field Name (ID): Description Reserved (RSVD): Reserved. ECCDIS: 0: ECC capable 1: Not ECC capable Reserved (RSVD): Reserved.
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Dynamic Power Performance Management (DPPM) Registers 5.3 Capabilities B (CAPID0)—Offset E8h Control of bits in this register are only required for customer visible SKU differentiation.
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Dynamic Power Performance Management (DPPM) Registers Bit Range Default & Access Field Name (ID): Description 19 0h RO Reserved (RSVD): Reserved. 18 0h RO_V ADDGFXEN: 0: Additive Graphics Disabled 1: Additive Graphics Enabled 17 0h RO_V ADDGFXCAP: 0: Capable of Additive Graphics 1: Not capable of Additive Graphics 16 0h RO Reserved (RSVD): Reserved. 15 0h RO_V DMIG3DIS: DMI Gen 3 Disable fuse. 0h RO Reserved (RSVD): Reserved.
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DMIBAR Registers 6 DMIBAR Registers Table 6-1.
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DMIBAR Registers 6.1 DMI Virtual Channel Enhanced Capability (DMIVCECH)—Offset 0h Indicates DMI Virtual Channel capabilities. Access Method Type: MEM (Size: 32 bits) Offset: [B:0, D:0, F:0] + 0h Default: 4010002h 0 0 0 1 6.
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DMIBAR Registers 0 0 0 0 0 0 0 0 0 1 6 0 0 0 0 1 2 0 0 0 0 8 0 0 0 0 4 0 0 Bit Range 0 Default & Access 0 0 0 0 Field Name (ID): Description 31:7 0h RO Reserved (RSVD): Reserved. 6:4 0h RO LPEVCC: Low Priority Extended VC Count: Indicates the number of (extended) Virtual Channels in addition to the default VC belonging to the low-priority VC (LPVC) group that has the lowest priority with respect to other VC resources in a strict-priority VC Arbitration.
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DMIBAR Registers 6.4 Bit Range Default & Access 31:24 0h RO VCATO: Reserved for VC Arbitration Table Offset: 23:8 0h RO Reserved (RSVD): Reserved.
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DMIBAR Registers 6.5 DMI VC0 Resource Capability (DMIVC0RCAP)— Offset 10h Access Method Type: MEM (Size: 32 bits) Offset: [B:0, D:0, F:0] + 10h Default: 1h 0 142 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 4 0 0 0 0 0 0 0 0 1 PAC 0 1 2 RSVD 0 1 6 REJSNPT 0 2 0 MTS 0 2 4 PATO 0 2 8 RSVD 3 1 Bit Range Default & Access 31:24 0h RO PATO: Reserved for Port Arbitration Table Offset: 23 0h RO Reserved (RSVD): Reserved.
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DMIBAR Registers 6.6 DMI VC0 Resource Control (DMIVC0RCTL)—Offset 14h Controls the resources associated with PCI Express Virtual Channel 0.
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DMIBAR Registers 6.7 DMI VC0 Resource Status (DMIVC0RSTS)—Offset 1Ah Reports the Virtual Channel specific status. Access Method Type: MEM (Size: 16 bits) Offset: [B:0, D:0, F:0] + 1Ah Default: 2h 0 0 8 0 0 0 0 4 0 0 0 0 Bit Range 0 1 0 Field Name (ID): Description 0h RO Reserved (RSVD): Reserved. 1 1h RO_V VC0NP: Virtual Channel 0 Negotiation Pending: 0: The VC negotiation is complete. 1: The VC resource is still in the process of negotiation (initialization or disabling).
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DMIBAR Registers 6.8 DMI VC1 Resource Capability (DMIVC1RCAP)— Offset 1Ch Access Method Type: MEM (Size: 32 bits) Offset: [B:0, D:0, F:0] + 1Ch Default: 8001h 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 8 0 0 0 0 4 0 0 0 0 0 0 0 0 1 PAC 0 1 2 RSVD 0 1 6 REJSNPT 0 2 0 MTS 0 2 4 PATO 0 2 8 RSVD 3 1 Bit Range Default & Access 31:24 0h RO PATO: Reserved for Port Arbitration Table Offset: 23 0h RO Reserved (RSVD): Reserved.
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DMIBAR Registers 6.9 DMI VC1 Resource Control (DMIVC1RCTL)—Offset 20h Controls the resources associated with PCI Express Virtual Channel 1. Access Method Type: MEM (Size: 32 bits) Offset: [B:0, D:0, F:0] + 20h Default: 1000100h Default & Access 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 4 0 0 0 0 0 0 0 0 0 TC0VC1M 1 8 TCVC1M 0 1 2 TCMVC1M 0 1 6 FC_FSM_STATE 0 RSVD Bit Range Field Name (ID): Description VC1E: Virtual Channel 1 Enable: 0: Virtual Channel is disabled.
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DMIBAR Registers Bit Range Default & Access 0h RO 7 6.10 Field Name (ID): Description TCMVC1M: Traffic Class m / Virtual Channel 1: 6:1 0h RW TCVC1M: Traffic Class / Virtual Channel 1 Map: Indicates the TCs (Traffic Classes) that are mapped to the VC resource. Bit locations within this field correspond to TC values. For example, when bit 6 is set in this field, TC6 is mapped to this VC resource.
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DMIBAR Registers 6.11 DMI VCm Resource Capability (DMIVCMRCAP)— Offset 34h Access Method Type: MEM (Size: 32 bits) Offset: [B:0, D:0, F:0] + 34h Default: 8000h 0 0 0 0 0 0 2 0 0 0 0 0 1 6 0 0 0 0 148 1 2 1 0 0 0 8 0 0 0 0 4 0 0 0 0 0 0 0 0 0 RSVD 0 2 4 RSVD 0 2 8 REJSNPT 3 1 Bit Range Default & Access 31:16 0h RO Reserved (RSVD): Reserved.
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DMIBAR Registers 6.12 DMI VCm Resource Control (DMIVCMRCTL)— Offset 38h Access Method Type: MEM (Size: 32 bits) Offset: [B:0, D:0, F:0] + 38h Default: 7000180h 0 RSVD 0 Bit Range 1 1 Default & Access 1 2 0 0 0 0 0 1 6 0 0 0 0 1 2 0 0 0 0 8 0 0 0 1 4 1 0 0 0 0 0 0 0 0 TCVCMMAP 0 VCID 0 VCMEN 0 2 4 FC_FSM_STATE 2 8 RSVD 3 1 Field Name (ID): Description 31 0h RW VCMEN: Virtual Channel enable: 0: Virtual Channel is disabled. 1: Virtual Channel is enabled.
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DMIBAR Registers 6.13 DMI VCm Resource Status (DMIVCMRSTS)—Offset 3Eh Access Method Type: MEM (Size: 16 bits) Offset: [B:0, D:0, F:0] + 3Eh Default: 2h 0 0 8 0 0 0 0 4 0 0 0 0 Bit Range 0 1 0 Field Name (ID): Description 0h RO Reserved (RSVD): Reserved. 1 1h RO_V VCNEGPND: Virtual Channel Negotiation Pending: 0: The VC negotiation is complete. 1: The VC resource is still in the process of negotiation (initialization or disabling).
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DMIBAR Registers 6.14 DMI Root Complex Link Declaration (DMIRCLDECH)—Offset 40h This capability declares links from the respective element to other elements of the root complex component to which it belongs and to an element in another root complex component. See PCI Express specification for link/topology declaration requirements.
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DMIBAR Registers 6.15 DMI Element Self Description (DMIESD)—Offset 44h Provides information about the root complex element containing this Link Declaration Capability.
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DMIBAR Registers 6.16 DMI Link Entry 1 Description (DMILE1D)—Offset 50h First part of a Link Entry which declares an internal link to another Root Complex Element.
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DMIBAR Registers 6.17 DMI Link Entry 1 Address (DMILE1A)—Offset 58h Second part of a Link Entry which declares an internal link to another Root Complex Element.
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DMIBAR Registers Bit Range 31:8 7:0 6.19 Default & Access Field Name (ID): Description 0h RO Reserved (RSVD): Reserved. 0h RW_O ULA: Upper Link Address: Memory mapped base address of the RCRB that is the target element (egress port of PCH) for this link entry. DMI Link Entry 2 Description (DMILE2D)—Offset 60h First part of a Link Entry which declares an internal link to another Root Complex Element.
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DMIBAR Registers 6.20 DMI Link Entry 2 Address (DMILE2A)—Offset 68h Second part of a Link Entry which declares an internal link to another Root Complex Element.
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DMIBAR Registers 0 0 1 0 0 0 0 0 1 1 0 1 0 1 1 0 0 0 1 0 0 0 0 0 1 1 MLS 0 4 MLW 0 8 ASLPMS 0 1 2 L0SELAT 0 1 6 L1SELAT 0 2 0 RSVD 0 2 4 RSVD 0 2 8 ASPM_OPT_COMPLIANCE 3 1 Bit Range Default & Access 31:23 0h RO Reserved (RSVD): Reserved. 22 1h RO ASPM_OPT_COMPLIANCE: ASPM Optionality Compliance. This bit should be set to 1b in all Functions. Components implemented against certain earlier versions of this specification will have this bit set to 0b.
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DMIBAR Registers 6.22 Link Control (LCTL)—Offset 88h Allows control of PCI Express link. Access Method Type: MEM (Size: 16 bits) Offset: [B:0, D:0, F:0] + 88h Default: 0h 0 0 0 0 0 0 0 0 ASPM 0 RSVD 0 RL 0 0 Bit Range Default & Access 15:10 0h RO Reserved (RSVD): Reserved.
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DMIBAR Registers 6.23 DMI Link Status (LSTS)—Offset 8Ah Indicates DMI status. Access Method Type: MEM (Size: 16 bits) Offset: [B:0, D:0, F:0] + 8Ah Default: 1h 0 0 0 0 0 0 0 0 0 0 0 0 1 NSPD 0 4 NWID 0 8 RSVD 0 RSVD 0 12 LTRN 15 Bit Range Default & Access 15:12 0h RO Reserved (RSVD): Reserved.
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DMIBAR Registers 6.24 Link Control 2 (LCTL2)—Offset 98h Access Method Type: MEM (Size: 16 bits) Offset: [B:0, D:0, F:0] + 98h Default: 1h Bit Range 0 0 0 0 0 0 0 0 1 TLS 0 EC 0 HASD 0 selectabledeemphasis 0 4 Field Name (ID): Description 0h RWS ComplianceDeemphasis: Compliance De-emphasis: For 8 GT/s Data Rate: This field sets the Transmitter Preset level in Polling.Compliance state if the entry occurred due to the Enter Compliance bit being 1b.
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DMIBAR Registers Bit Range Default & Access Field Name (ID): Description 0h RWS_V txmargin: Transmit Margin: This field controls the value of the non-deemphasized voltage level at the Transmitter pins. This field is reset to 000b on entry to the LTSSM Polling.Configuration substrate. 000: Normal operating range 001: 800-1200 mV for full swing and 400-700 mV for half-swing 010 - (n-1): Values should be monotonic with a non-zero slope. The value of n should be greater than 3 and less than 7.
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DMIBAR Registers 6.25 Link Status 2 (LSTS2)—Offset 9Ah Access Method Type: MEM (Size: 16 bits) Offset: [B:0, D:0, F:0] + 9Ah Default: 0h 0 0 Bit Range 0 0 0 0 0 0 0 Field Name (ID): Description 0h RO Reserved (RSVD): Reserved. 5 0h RW1C LNKEQREQ: This bit is Set by hardware to request the Link equalization process to be performed on the Link.
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DMIBAR Registers 6.26 DMI Uncorrectable Error Status (DMIUESTS)— Offset 1C4h DMI Uncorrectable Error Status register. This register is for test and debug purposes only. Access Method Type: MEM (Size: 32 bits) Offset: [B:0, D:0, F:0] + 1C4h Default: 0h 0 0 0 0 0 0 0 0 Bit Range Default & Access 31:21 0h RO Reserved (RSVD): Reserved. 20 0h RW1CS URES: Unsupported Request Error Status: 19 0h RO Reserved (RSVD): Reserved.
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DMIBAR Registers 6.27 DMI Uncorrectable Error Mask (DMIUEMSK)— Offset 1C8h DMI Uncorrectable Error Mask register. This register is for test and debug purposes only. Access Method Type: MEM (Size: 32 bits) Offset: [B:0, D:0, F:0] + 1C8h Default: 0h 164 0 0 0 0 0 0 Bit Range Default & Access 31:23 0h RO Reserved (RSVD): Reserved. 22 0h RWS ECCERRM: 2 Bit Error Mask: 21 0h RO Reserved (RSVD): Reserved.
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DMIBAR Registers Bit Range 11:5 4 3:0 6.28 Default & Access Field Name (ID): Description 0h RO Reserved (RSVD): Reserved. 0h RWS DLPEM: Data Link Protocol Error Mask: 0h RO Reserved (RSVD): Reserved. DMI Uncorrectable Error Severity (DMIUESEV)— Offset 1CCh DMI Uncorrectable Error Severity register. This register controls whether an individual error is reported as a non-fatal or fatal error. An error is reported as fatal when the corresponding error bit in the severity register is set.
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DMIBAR Registers Bit Range Field Name (ID): Description 16 0h RWS UCES: Unexpected Completion Error Severity: 15 0h RO CAES: Reserved for Completer Abort Error Severity: 14 0h RWS CTES: Completion Timeout Error Severity: 13 0h RO FCPES: Reserved for Flow Control Protocol Error Severity: 12 0h RWS PTLPES: Poisoned TLP Error Severity: 0h RO Reserved (RSVD): Reserved. 1h RWS DLPES: Data Link Protocol Error Severity: 0h RO Reserved (RSVD): Reserved. 11:5 4 3:0 6.
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DMIBAR Registers Bit Range Field Name (ID): Description 8 0h RW1CS RNRS: REPLAY_NUM Rollover Status: 7 0h RW1CS BDLLPS: Bad DLLP Status: 6 0h RW1CS BTLPS: Bad TLP Status: 0h RO Reserved (RSVD): Reserved. 0h RW1CS RES: Receiver Error Status: Physical layer receiver Error occurred. These errors include: elastic Buffer Collision, 8b/10b error, De-skew Timeout Error. 5:1 0 6.30 Default & Access DMI Correctable Error Mask (DMICEMSK)—Offset 1D4h DMI Correctable Error Mask register.
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MCHBAR Registers 7 MCHBAR Registers Table 7-1.
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MCHBAR Registers Table 7-1.
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MCHBAR Registers Table 7-1.
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MCHBAR Registers 7.2 Bit Range Default & Access 30:24 0h RO tWRPRE: Holds DDR timing parameter tWRPRE. WR to PRE same bank minimum delay in DCLK cycles. Note: tWRRD_sg+tRDPRE should be greater than or equal to tWRPRE Supported range is 23-95. 19:16 0h RO tRDPRE: Holds DDR timing parameter tRDPRE. RD to PRE same bank minimum delay in DCLK cycles. Supported range is 6-15. 14:8 0h RO tRAS: Holds DDR timing parameter tRAS. ACT to PRE same bank minimum delay in DCLK cycles. Supported range is 28-64.
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MCHBAR Registers Bit Range 172 Default & Access Field Name (ID): Description 31:29 0h RO tCAL: For DDR4, holds tCAL value. Supported values: 0 (CAL mode disabled), 3-5 (CAL mode enabled, value is the delay in DCLK cycles from CSb to command). Updating this field is required only after sending MRS to MR4 enabling/disabling CAL mode before any other command is sent to DRAM. TC_MR4_shaddow_0_0_0_MCHBAR should be updated with the correct value of tCAL once its value changes.
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MCHBAR Registers 7.
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MCHBAR Registers Bit Range 10:8 6:4 2:0 7.4 Default & Access Field Name (ID): Description 0h RO ODT_write_duration: Controls the length of the ODT pulse for write commands. Default is 6 DCLK cycles (BL/2 + 2) 000: 6 DCLK cycles 001: 7 DCLK cycles 010: 8 DCLK cycles 011: 9 DCLK cycles 100: 10 DCLK cycles 101: 11 DCLK cycles 110: 12 DCLK cycles 111: 13 DCLK cycles 0h RO ODT_Read_Delay: Controls delay from RD-CAS to ODT assertion in DCLK cycles (Typical Programming = tCL-tCWL).
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MCHBAR Registers 7.5 Bit Range Default & Access 31:25 23h RW_L tREFIx9: Maximum time allowed between refreshes to a rank (in intervals of 1024 DCLK cycles). Should be programmed to 8.9*tREFI/1024 (to allow for possible delays from ZQ or isoc). 24:16 0h RO Reserved (RSVD): Reserved. 15:12 9h RW_L Refresh_panic_wm: tREFI count level in which the refresh priority is panic (default is 9). The Maximum value for this field is 9.
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MCHBAR Registers 7.6 Power Management DIMM Idle Energy (PM)— Offset 4260h This register defines the energy of an idle DIMM with CKE on. Each 6-bit field corresponds to an integer multiple of the base DRAM command energy for that DIMM. There are two 6-bit fields, one per DIMM.
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MCHBAR Registers 7.7 Power Management DIMM Power Down Energy (PM)—Offset 4264h This register defines the energy of an idle DIMM with CKE off. Each 6-bit field corresponds to an integer multiple of the base DRAM command energy for that DIMM. There are two 6-bit fields, one per DIMM.
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MCHBAR Registers 7.8 Power Management DIMM Activate Energy (PM)— Offset 4268h This register defines the combined energy contribution of activate and precharge commands. Each 8-bit field corresponds to an integer multiple of the base DRAM command energy for that DIMM. There are 2 8-bit fields, one per DIMM.
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MCHBAR Registers 7.9 Power Management DIMM RdCas Energy (PM)— Offset 426Ch This register defines the energy contribution of a read CAS command. Each 8-bit field corresponds to an integer multiple of the base DRAM command energy for that DIMM. There are 2 8-bit fields, one per DIMM.
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MCHBAR Registers 7.10 Power Management DIMM WrCas Energy (PM)— Offset 4270h This register defines the energy contribution of a write CAS command. Each 8-bit field corresponds to an integer multiple of the base DRAM command energy for that DIMM. There are 2 8-bit fields, one per DIMM.
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MCHBAR Registers 7.11 MCHBAR_CH1_CR_TC_PRE_0_0_0_MCHBAR— Offset 4400h DDR timing constraints related to PRE commands Access Method Type: MEM (Size: 32 bits) Offset: [B:0, D:0, F:0] + 4400h Default: 0h 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 4 0 0 0 0 0 0 0 0 0 tRP 0 tWRPRE 0 1 2 tRPab 0 1 6 tRAS 0 2 0 RSVD 0 RSVD 0 2 4 tRDPRE 2 8 RSVD 3 1 Bit Range Default & Access 30:24 0h RO tWRPRE: Holds DDR timing parameter tWRPRE.
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MCHBAR Registers 7.
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MCHBAR Registers Bit Range Default & Access 22:20 0h RO reset_delay: Inserts an N Dclk delay ranging from 0 to 7 after the N to 1 Reset on Cmd is triggered. 19:16 0h RO reset_on_command: The N:1 logic can be triggered to insert a bubble and reset the N:1 logic after a programmable delay from a command after a PRE/ACT/RD/WR CMD. This allows one to synchronize the N:1 logic periodically to ensure the correct worst case pattern between victim and aggressor occurs when training the command bus.
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MCHBAR Registers 7.
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MCHBAR Registers Bit Range 10:8 6:4 2:0 7.14 Default & Access Field Name (ID): Description 0h RO ODT_write_duration: Controls the length of the ODT pulse for write commands. Default is 6 DCLK cycles (BL/2 + 2) 000: 6 DCLK cycles 001: 7 DCLK cycles 010: 8 DCLK cycles 011: 9 DCLK cycles 100: 10 DCLK cycles 101: 11 DCLK cycles 110: 12 DCLK cycles 111: 13 DCLK cycles 0h RO ODT_Read_Delay: Controls delay from RD-CAS to ODT assertion in DCLK cycles (Typical Programming = tCL-tCWL).
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MCHBAR Registers 7.15 Bit Range Default & Access 31:25 23h RW_L tREFIx9: Maximum time allowed between refreshes to a rank (in intervals of 1024 DCLK cycles). Should be programmed to 8.9*tREFI/1024 (to allow for possible delays from ZQ or isoc). 24:16 0h RO Reserved (RSVD): Reserved. 15:12 9h RW_L Refresh_panic_wm: tREFI count level in which the refresh priority is panic (default is 9). The Maximum value for this field is 9.
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MCHBAR Registers 7.16 Power Management DIMM Idle Energy (PM)— Offset 4660h This register defines the energy of an idle DIMM with CKE on. Each 6-bit field corresponds to an integer multiple of the base DRAM command energy for that DIMM. There are 2 6-bit fields, one per DIMM.
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MCHBAR Registers 7.17 Power Management DIMM Power Down Energy (PM)—Offset 4664h This register defines the energy of an idle DIMM with CKE off. Each 6-bit field corresponds to an integer multiple of the base DRAM command energy for that DIMM. There are 2 6-bit fields, one per DIMM.
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MCHBAR Registers 7.18 Power Management DIMM Activate Energy (PM)— Offset 4668h This register defines the combined energy contribution of activate and precharge commands. Each 8-bit field corresponds to an integer multiple of the base DRAM command energy for that DIMM. There are 2 8-bit fields, one per DIMM.
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MCHBAR Registers 7.19 Power Management DIMM RdCas Energy (PM)— Offset 466Ch This register defines the energy contribution of a read CAS command. Each 8-bit field corresponds to an integer multiple of the base DRAM command energy for that DIMM. There are 2 8-bit fields, one per DIMM.
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MCHBAR Registers 7.20 Power Management DIMM WrCas Energy (PM)— Offset 4670h This register defines the energy contribution of a write CAS command. Each 8-bit field corresponds to an integer multiple of the base DRAM command energy for that DIMM. There are 2 8-bit fields, one per DIMM.
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MCHBAR Registers 7.21 MCSCHEDS_CR_SC_GS_CFG_0_0_0_MCHBAR— Offset 4C1Ch Scheduler configuration. Access Method Type: MEM (Size: 32 bits) Offset: [B:0, D:0, F:0] + 4C1Ch Default: 0h 0 0 0 0 0 0 2 0 0 0 0 0 1 6 0 0 0 0 1 2 0 0 0 0 8 0 0 0 0 Bit Range 31:4 3:2 1:0 192 Default & Access 0h RO 0h RW_L 0h RO 4 0 0 0 0 0 0 0 0 0 RSVD 0 2 4 RSVD 0 2 8 CMD_strech 3 1 Field Name (ID): Description Reserved (RSVD): Reserved.
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MCHBAR Registers 7.
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MCHBAR Registers 7.23 MCSCHEDS_CR_TC_ODT_0_0_0_MCHBAR—Offset 4C70h ODT timing related parameters. Access Method Type: MEM (Size: 32 bits) Offset: [B:0, D:0, F:0] + 4C70h Default: 0h 0 0 0 0 Default & Access 31:26 0h RO 20:16 15:0 194 0 0 tCWL Bit Range 25:21 0 2 0 6h RW_L 0 0 0 1 6 0 0 0 0 1 2 0 0 0 0 8 0 0 0 0 4 0 0 0 0 0 0 0 0 0 RSVD 0 2 4 RSVD 0 2 8 tCL 3 1 Field Name (ID): Description Reserved (RSVD): Reserved.
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MCHBAR Registers 7.24 Refresh parameters (TC)—Offset 4E38h Refresh parameters Access Method Type: MEM (Size: 32 bits) Offset: [B:0, D:0, F:0] + 4E38h Default: 4600980Fh 0 1 1 0 0 0 0 0 0 0 0 0 1 2 1 0 0 1 8 1 0 0 0 4 0 0 0 0 0 1 1 1 1 OREF_RI 0 1 6 Refresh_HP_WM 0 2 0 Refresh_panic_wm 1 2 4 tREFIx9 0 2 8 RSVD 3 1 Bit Range Default & Access 31:25 23h RW_L tREFIx9: Maximum time allowed between refreshes to a rank (in intervals of 1024 DCLK cycles).
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MCHBAR Registers 7.25 Refresh timing parameters (TC)—Offset 4E3Ch Refresh timing parameters Access Method Type: MEM (Size: 32 bits) Offset: [B:0, D:0, F:0] + 4E3Ch Default: B41004h 0 0 0 0 7.26 0 0 2 0 1 0 1 1 1 6 0 1 0 0 1 2 0 0 0 1 8 0 0 tRFC 0 2 4 RSVD 0 2 8 0 0 4 0 0 0 0 0 0 1 0 0 tREFI 3 1 Bit Range Default & Access 31:26 0h RO Reserved (RSVD): Reserved.
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MCHBAR Registers 0 0 0 0 0 0 2 0 0 0 0 0 1 6 0 0 0 0 1 2 0 0 0 0 0 0 0 DIMM1_IDLE_ENERGY 0 4 0 0 0 0 0 0 0 0 Bit Range Default & Access 31:14 0h RO Reserved (RSVD): Reserved. 0h RW_L DIMM1_IDLE_ENERGY: This register defines the energy consumed by DIMM1 for one clock cycle when the DIMM is idle with cke on 7:6 0h RO Reserved (RSVD): Reserved.
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MCHBAR Registers Bit Range Default & Access 31:14 0h RO Reserved (RSVD): Reserved. 0h RW_L DIMM1_PD_ENERGY: This register defines the energy consumed by DIMM1 for one clock cycle when the DIMM is idle with cke off 7:6 0h RO Reserved (RSVD): Reserved. 5:0 0h RW_L DIMM0_PD_ENERGY: This register defines the energy consumed by DIMM0 for one clock cycle when the DIMM is idle with cke off 13:8 7.
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MCHBAR Registers 7.29 Power Management DIMM RdCas Energy (PM)— Offset 4E6Ch This register defines the energy contribution of a read CAS command. Each 8-bit field corresponds to an integer multiple of the base DRAM command energy for that DIMM. There are 2 8-bit fields, one per DIMM.
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MCHBAR Registers 7.30 Power Management DIMM WrCas Energy (PM)— Offset 4E70h This register defines the energy contribution of a write CAS command. Each 8-bit field corresponds to an integer multiple of the base DRAM command energy for that DIMM. There are 2 8-bit fields, one per DIMM.
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MCHBAR Registers 7.31 Address decoder inter channel configuration register (MAD)—Offset 5000h This register holds parameters used by the channel decode stage. It defines virtual channel L mapping, as well as channel S size. Also defined is the DDR type installed in the system (DDR4 or DDR3).
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MCHBAR Registers 7.32 Address decoder intra channel configuration register (MAD)—Offset 5004h This register holds parameters used by the DRAM decode stage. Access Method Type: MEM (Size: 32 bits) Offset: [B:0, D:0, F:0] + 5004h Default: 0h Bit Range Default & Access 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIMM_L_MAP 0 0 RSVD 0 RI 0 4 RSVD 0 8 EIM 0 1 2 RSVD 0 1 6 ECC 0 2 0 Field Name (ID): Description 0h RO Reserved (RSVD): Reserved.
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MCHBAR Registers Bit Range Field Name (ID): Description RI: Rank interleaving enable bit 0: Disabled 1: Enabled 0h RW_L 4 0h RO 3:1 Reserved (RSVD): Reserved. DIMM_L_MAP: Virtual DIMM L mapping to physical DIMM 0: DIMM0 1: DIMM1 0h RW_L 0 7.33 Default & Access Address decoder intra channel configuration register (MAD)—Offset 5008h This register holds parameters used by the DRAM decode stage.
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MCHBAR Registers Bit Range Default & Access 13:12 0h RW_L Reserved (RSVD): Reserved. 0h RO Reserved (RSVD): Reserved. 11:9 8 7:5 4 0h RW_L EIM: Enhanced mode enable bit 0: Disabled 1: Enabled 0h RO Reserved (RSVD): Reserved. 0h RW_L RI: Rank interleaving enable bit 0: Disabled 1: Enabled 0h RO 3:1 Reserved (RSVD): Reserved. DIMM_L_MAP: Virtual DIMM L mapping to physical DIMM 0: DIMM0 1: DIMM1 0h RW_L 0 7.34 Field Name (ID): Description Address decode DIMM parameters.
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MCHBAR Registers Bit Range Default & Access 31:28 0h RO Reserved (RSVD): Reserved. 27 0h RW_L DS8Gb: Defines whether DIMM S is built from 8Gb DRAM modules. 0: Not 8Gb 1: 8Gb 26 0h RW_L DSNOR: DIMM S number of ranks 0: 1 Rank 1: 2 Ranks 25:24 0h RW_L DSW: DSW: DIMM S width of DDR chips 00: X8 chips 01: X16 chips 10: X32 chips 11: Reserved 23:22 0h RO Reserved (RSVD): Reserved. 21:16 0h RW_L DIMM_S_SIZE: Size of DIMM S in 1GB multiples 15:12 0h RO Reserved (RSVD): Reserved.
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MCHBAR Registers 7.35 Address decode DIMM parameters (MAD)—Offset 5010h This register defines channel DIMM characteristics - number of DIMMs, number of ranks, size and type. Access Method Type: MEM (Size: 32 bits) Offset: [B:0, D:0, F:0] + 5010h Default: 0h 206 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Range Default & Access 31:28 0h RO Reserved (RSVD): Reserved. 27 0h RW_L DS8Gb: Defines whether DIMM S is built from 8Gb DRAM modules.
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MCHBAR Registers Bit Range 7.36 Default & Access Field Name (ID): Description 9:8 0h RW_L DLW: DLW: DIMM L width of DDR chips 00: X8 chips 01: X16 chips 10: X32 chips 11: Reserved 7:6 0h RO Reserved (RSVD): Reserved. 5:0 0h RW_L DIMM_L_SIZE: Size of DIMM L in 1GB multiples MCDECS_CR_MRC_REVISION_0_0_0_MCHBAR_MCMA IN—Offset 5034h Scheduler configuration.
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MCHBAR Registers combined to a single 64-byte data transfers from DRAM. Therefore multiplying the number of requests by 64-bytes will lead to inaccurate GT memory bandwidth. The inaccuracy is proportional to the number of same-cache-line partial writes combined.
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MCHBAR Registers Bit Range Field Name (ID): Description 0h RW_LV 31:0 7.39 Default & Access count: Number of accesses Request count from IO (DRAM)—Offset 5048h Counts every read/write request entering the Memory Controller to DRAM (sum of all channels) from all IO sources (e.g. PCIe, Display Engine, USB audio, etc.). Each partial write request counts as a request incrementing this counter. However same-cache-line partial write requests are combined to a single 64-byte data transfers from DRAM.
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MCHBAR Registers 3 1 0 0 0 2 4 0 0 0 0 2 0 0 0 0 0 1 6 0 0 0 0 1 2 0 0 0 0 8 0 0 0 0 4 0 0 0 0 0 0 0 0 0 count 0 2 8 Bit Range Field Name (ID): Description 0h RW_LV 31:0 7.41 Default & Access count: Number of accesses WR data count (DRAM)—Offset 5054h Counts every write (WrCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64-byte data transfers from DRAM. Use for accurate memory bandwidth calculations.
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MCHBAR Registers 7.42 Self refresh configuration Register (PM)—Offset 5060h Self refresh mode control register - defines if and when DDR can go into SR Access Method Type: MEM (Size: 32 bits) Offset: [B:0, D:0, F:0] + 5060h Default: 10200h 0 0 0 0 0 0 7.43 2 0 0 0 0 0 1 6 0 0 0 1 1 2 0 0 0 0 8 0 0 1 0 4 0 0 0 0 0 0 0 0 0 Idle_timer 0 2 4 RSVD 0 2 8 SR_Enable 3 1 Bit Range Default & Access 31:17 0h RO Reserved (RSVD): Reserved.
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MCHBAR Registers 6 3 6 0 5 6 5 2 4 8 4 4 4 0 3 6 3 2 2 8 2 4 2 0 1 6 1 2 8 4 0 7.44 GFXVTBAREN RSVD RSVD GFXVTBAR 0000000000000000000000000000000000000000000000000000000000000000 Bit Range Default & Access 38:12 0h RO GFXVTBAR: This field corresponds to bits 38 to 12 of the base address GFX-VT configuration space. BIOS will program this register resulting in a base address for a 4KB block of contiguous memory address space.
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MCHBAR Registers Bit Range 7.45 Default & Access Field Name (ID): Description 38:12 0h RO VTVC0BAR: This field corresponds to bits 38 to 12 of the base address DMI/PEG VC0 configuration space. BIOS will program this register resulting in a base address for a 4KB block of contiguous memory address space. This register ensures that a naturally aligned 4KB space is allocated within the first 512GB of addressable memory space.
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MCHBAR Registers Bit Range 214 Default & Access Field Name (ID): Description 31:25 0h RW TEMPERATURE_AVERAGING_TIME_WINDOW: averaging window for the running exponential average temperature. x = 2 msbs, that is [31:30] y = 5 lsbs, that is [29:25] The timing interval window is Floating Point number given by 1.x * power(2,y). The unit of measurement is defined in PACKAGE_POWER_SKU_UNIT_MSR[TIME_UNIT]. A value of zero means no averaging.
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MCHBAR Registers 7.46 PKG—Offset 5828h Sum the cycles per number of active cores Access Method Type: MEM (Size: 64 bits) Offset: [B:0, D:0, F:0] + 5828h Default: 0h 6 3 6 0 5 6 5 2 4 8 4 4 4 0 3 6 3 2 2 8 2 4 2 0 1 6 1 2 8 4 0 DATA 0000000000000000000000000000000000000000000000000000000000000000 Bit Range 63:0 7.47 Default & Access Field Name (ID): Description DATA: RO: The counter value is incremented as a function of the number of cores that reside in C0 and active.
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MCHBAR Registers 7.48 PKG—Offset 5838h Sum the cycles of active GT Access Method Type: MEM (Size: 64 bits) Offset: [B:0, D:0, F:0] + 5838h Default: 0h 6 3 6 0 5 6 5 2 4 8 4 4 4 0 3 6 3 2 2 8 2 4 2 0 1 6 1 2 8 4 0 DATA 0000000000000000000000000000000000000000000000000000000000000000 Bit Range 63:0 7.49 Default & Access 0h ROV Field Name (ID): Description DATA: RO, This counter increments whenever GT slices or un slices are active and in C0 state.
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MCHBAR Registers 7.50 PKG—Offset 5848h Sum the cycles of any active GT slice. Access Method Type: MEM (Size: 64 bits) Offset: [B:0, D:0, F:0] + 5848h Default: 0h 6 3 6 0 5 6 5 2 4 8 4 4 4 0 3 6 3 2 2 8 2 4 2 0 1 6 1 2 8 4 0 DATA 0000000000000000000000000000000000000000000000000000000000000000 Bit Range 63:0 7.51 Default & Access 0h ROV Field Name (ID): Description DATA: RO, This counter increments whenever any GT slice is active.
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MCHBAR Registers 7.52 DDR—Offset 5880h Mode control bits for DDR power and thermal management features. Access Method Type: MEM (Size: 32 bits) Offset: [B:0, D:0, F:0] + 5880h Default: 0h 0 0 0 0 0 0 0 0 Bit Range 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Field Name (ID): Description 0h RO Reserved (RSVD): Reserved. 8 0h RW DDR4_SKIP_REFRESH_EN: DDR4 DRAM supports temperature controlled refresh and self refresh.
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MCHBAR Registers Bit Range 3:2 1 0 7.53 Default & Access Field Name (ID): Description 0h RW REFRESH_2X_MODE: These bits are read by reset hardware and later broadcast (together with the thermal status) into the iMC cregs that control 2x refresh modes. When DRAM is hot, it accumulates bits errors more quickly. The iMC refresh mechanism is how those errors get prevented and corrected (using ECC).
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MCHBAR Registers Bit Range 31:3 2:0 7.54 Default & Access Field Name (ID): Description 0h RO Reserved (RSVD): Reserved. 3h RW SCALEFACTOR: Defines the base DDR energy unit of 2^(-30-scalefactor) Joules. The values are defined as follows: 0d0 = 3'b000 = 931.3pJ, 0d1 = 3'b001 = 465.7pJ, 0d2 = 3'b010 = 232.8pJ, 0d3 = 3'b011 = 116.4pJ, 0d4 = 3'b100 = 58.2pJ, 0d5 = 3'b101 = 29.1pJ, 0d6 = 3'b110 = 14.6pJ, 0d7 = 3'b111 = 7.3pJ. The default reset value is 0d3 = 3'b011 = 116.4pJ.
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MCHBAR Registers 7.55 DDR—Offset 588Ch Per-DIMM thermal status values. The encoding of each DIMM thermal status is the same: 2'b00 = COLD, 2'b01 = WARM, 2'b11 = HOT, 2'b10 == Reserved. Access Method Type: MEM (Size: 32 bits) Offset: [B:0, D:0, F:0] + 588Ch Default: 0h 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 Bit Range Default & Access 31:12 0h RO Reserved (RSVD): Reserved.
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MCHBAR Registers 7.56 DDR—Offset 5890h Per-DIMM temp/power thresholds used for CLTM/OLTM thermal status computation. These values can impact iMC throttling and memory thermal interrupts. Access Method Type: MEM (Size: 32 bits) Offset: [B:0, D:0, F:0] + 5890h Default: FFFFh 0 0 0 0 0 0 2 0 0 0 0 0 1 6 0 0 0 0 1 2 1 1 1 7.57 1 8 1 1 1 1 4 1 1 1 1 0 1 1 1 1 DIMM0 0 2 4 RSVD 0 2 8 DIMM1 3 1 Bit Range Default & Access 31:16 0h RO Reserved (RSVD): Reserved.
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MCHBAR Registers 7.58 Bit Range Default & Access 31:16 0h RO Reserved (RSVD): Reserved. 15:8 FFh RWS_L DIMM1: WARM_THRESHOLD for DIMM1 on this channel. 7:0 FFh RWS_L DIMM0: WARM_THRESHOLD for DIMM0 on this channel. Field Name (ID): Description DDR—Offset 5898h Per-DIMM temp/power thresholds used for CLTM/OLTM thermal status computation. These values can impact iMC throttling and memory thermal interrupts.
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MCHBAR Registers 7.59 DDR—Offset 589Ch Per-DIMM temp/power thresholds used for CLTM/OLTM thermal status computation. These values can impact iMC throttling and memory thermal interrupts. Access Method Type: MEM (Size: 32 bits) Offset: [B:0, D:0, F:0] + 589Ch Default: FFFFh 0 0 0 0 0 0 2 0 0 0 0 0 1 6 0 0 0 0 7.60 1 2 1 1 1 1 8 1 1 1 1 Bit Range Default & Access 31:16 0h RO Reserved (RSVD): Reserved. 15:8 FFh RWS_L DIMM1: HOT_THRESHOLD for DIMM1 on this channel.
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MCHBAR Registers 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE_WARM_INTERRUPT 0 RSVD 0 RSVD 0 0 ENABLE_HOT_INTERRUPT 0 RSVD 0 ENABLE_2X_REFRESH_INTERRUPT 0 RSVD 0 4 ENABLE_OOS_TEMP_INTERRUPT 0 8 RSVD 0 1 2 ENABLE_THRESHOLD1_INTERRUPT 0 1 6 ENABLE_THRESHOLD2_INTERRUPT 0 2 0 RSVD 0 2 4 POLICY_FREE_THRESHOLD2 0 2 8 POLICY_FREE_THRESHOLD1 3 1 Bit Range Default & Access 31:24 0h RW POLICY_FREE_THRESHOLD2: A threshold temperature value used only for interr
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MCHBAR Registers Bit Range 7.61 Default & Access Field Name (ID): Description 4 0h RW ENABLE_2X_REFRESH_INTERRUPT: When set, interrupts will be generated on a rising transition of the hottest DIMM thermal status across whichever threshold 2x refresh is configured for (WARM_THRESHOLD, HOT_THRESHOLD, or never, depending on DDR_PTM_CTL.REFRESH_2X_MODE).
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MCHBAR Registers Bit Range Default & Access 31:16 0h RO Reserved (RSVD): Reserved. 7F00h RO_V THERM_MARGIN: Temperature margin in PECI temperature counts from the thermal profile specification. THERM_MARGIN is in 2's complement format (8.8 format where MSB equals 1 Sign bit + 7 bits of integer temperature value and the LSB equals 8 precision bits of temperature value). A value of zero indicates the hottest Processor die temperature is on the thermal profile line.
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MCHBAR Registers 7.63 DDR—Offset 58B4h Per-DIMM temperature values. Access Method Type: MEM (Size: 32 bits) Offset: [B:0, D:0, F:0] + 58B4h Default: 0h 0 0 0 0 0 0 2 0 0 0 0 0 1 6 0 0 0 0 1 2 0 0 7.64 0 0 8 0 0 0 0 4 0 0 Bit Range Default & Access 31:16 0h RO Reserved (RSVD): Reserved. 15:8 0h ROS DIMM1: Temperature of DIMM1 on this channel. 7:0 0h ROS DIMM0: Temperature of DIMM0 on this channel.
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MCHBAR Registers 7.65 Bit Range Default & Access 63:32 0h RO Reserved (RSVD): Reserved. 31:16 0h ROS DIMM1: Throttle duration of DIMM 1 on this channel, in units of 1/1024 seconds. 15:0 0h ROS DIMM0: Throttle duration of DIMM 0 on this channel, in units of 1/1024 seconds. Field Name (ID): Description DDR—Offset 58C8h Per-DIMM throttle duration counters.
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MCHBAR Registers 7.66 DDR—Offset 58D0h Per-DIMM power budget for MC thermal throttling when thermal status is WARM. Access Method Type: MEM (Size: 32 bits) Offset: [B:0, D:0, F:0] + 58D0h Default: FFFFh 0 0 0 0 0 0 2 0 0 0 0 0 1 6 0 0 0 0 1 2 1 1 1 7.67 1 8 1 1 1 1 4 1 1 1 1 0 1 1 1 1 DIMM0 0 2 4 RSVD 0 2 8 DIMM1 3 1 Bit Range Default & Access 31:16 0h RO Reserved (RSVD): Reserved. 15:8 FFh RWS_L DIMM1: WARM_BUDGET for DIMM1 on this channel.
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MCHBAR Registers 7.68 Bit Range Default & Access 31:16 0h RO Reserved (RSVD): Reserved. 15:8 FFh RWS_L DIMM1: WARM_BUDGET for DIMM1 on this channel. 7:0 FFh RWS_L DIMM0: WARM_BUDGET for DIMM0 on this channel. Field Name (ID): Description DDR—Offset 58D8h Per-DIMM power budget for MC thermal throttling when thermal status is HOT.
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MCHBAR Registers 7.69 DDR—Offset 58DCh Per-DIMM power budget for MC thermal throttling when thermal status is HOT. Access Method Type: MEM (Size: 32 bits) Offset: [B:0, D:0, F:0] + 58DCh Default: FFFFh 0 0 0 0 0 0 2 0 0 0 0 0 1 6 0 0 0 0 1 2 1 1 1 7.70 1 8 1 1 1 1 4 1 1 1 1 0 1 1 1 1 DIMM0 0 2 4 RSVD 0 2 8 DIMM1 3 1 Bit Range Default & Access 31:16 0h RO Reserved (RSVD): Reserved. 15:8 FFh RWS_L DIMM1: HOT_BUDGET for DIMM1 on this channel.
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MCHBAR Registers Bit Range Field Name (ID): Description COUNTS: Counter of the time units within which RAPL was limiting P-states. If limitation occurred anywhere within the time window of 1/1024 seconds, the count will be incremented (limitation on accuracy). This data can serve as a proxy for the potential performance impacts of RAPL on cores performance. 0h ROS_V 31:0 7.
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MCHBAR Registers Bit Range 234 Default & Access Field Name (ID): Description 26 0h RW0C PBM_PL1_LOG: PBM PL1 (pkg, platform) Log, RW, When set by hardware indicates that PBM PL1 (package or platform PL1) has cause IA frequency clipping. Software should write to this bit to clear the status in this bit 25 0h RW0C SPARE_IA_9_LOG: Reserved 24 0h RW0C OTHER_LOG: Other (IccMax, PL4, etc) Log, RW, When set by hardware indicates that other has cause reason IA frequency clipping.
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MCHBAR Registers Bit Range 7.
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MCHBAR Registers Bit Range 236 Default & Access Field Name (ID): Description 31 0h RW0C SPARE_GT_15_LOG: Reserved 30 0h RW0C SPARE_GT_14_LOG: Reserved 29 0h RW0C SPARE_GT_13_LOG: Reserved 28 0h RW0C INEFFICIENT_OPERATION_LOG: Inefficient operation Log, RW, The current GT Frequency lower than the DCC target Frequency.
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MCHBAR Registers Bit Range 7.
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MCHBAR Registers 7.74 Bit Range Default & Access 31:24 0h RO_V UCLK_RATIO: RING UCLK RATIO. Reference=100Mhz 23:16 0h RO_V ICLK_RATIO: IMGU ICLK RATIO. Reference=25Mhz 15:8 0h RO_V FCLK_RATIO: SA FCLK RATIO. Reference=100Mhz 7 0h RO_V QCLK_REFERENCE: DDR QCLK REFERENCE. 0=133Mhz, 1=100Mhz 6:0 0h RO_V QCLK_RATIO: DDR QCLK RATIO.
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MCHBAR Registers 7.75 EDRAM—Offset 594Ch EDRAM die temperature in degrees (C). Access Method Type: MEM (Size: 32 bits) This field is updated by FW. Offset: [B:0, D:0, F:0] + 594Ch Default: 0h 0 0 0 2 4 0 0 0 0 2 0 0 0 0 0 1 6 0 0 0 0 1 2 0 0 0 0 8 0 0 0 0 4 0 0 0 RSVD 0 2 8 Bit Range 31:8 7:0 7.76 0 0 0 0 0 0 DATA 3 1 Default & Access Field Name (ID): Description 0h RO Reserved (RSVD): Reserved. 0h RO_V DATA: Temperature in degrees (C).
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MCHBAR Registers 7.77 PP0—Offset 597Ch PP0 (IA) temperature in degrees (C). This field is updated by FW. Access Method Type: MEM (Size: 32 bits) Offset: [B:0, D:0, F:0] + 597Ch Default: 0h 0 0 0 2 4 0 0 0 0 2 0 0 0 0 0 1 6 0 0 0 0 1 2 0 0 0 0 8 0 0 0 0 4 0 0 0 RSVD 0 2 8 Bit Range 31:8 7:0 7.78 0 0 0 0 0 0 DATA 3 1 Default & Access Field Name (ID): Description 0h RO Reserved (RSVD): Reserved. 0h RO_V DATA: Temperature in degrees (C).
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MCHBAR Registers Bit Range 31:8 7:0 7.79 Default & Access Field Name (ID): Description 0h RO Reserved (RSVD): Reserved. 0h RO_V DATA: Temperature in degrees (C). RP—Offset 5994h This register allows SW to limit the maximum base frequency for the Integrated GFX Engine (GT) allowed during run-time.
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MCHBAR Registers 7.80 RP—Offset 5998h This register contains the maximum base frequency capability for the Integrated GFX Engine (GT). Access Method Type: MEM (Size: 32 bits) Offset: [B:0, D:0, F:0] + 5998h Default: 0h 0 0 0 242 0 0 0 0 0 0 1 6 0 0 0 0 1 2 0 0 0 0 8 0 0 0 0 4 0 0 0 0 0 0 0 0 0 RP0_CAP 0 2 0 RP1_CAP 0 2 4 RSVD 0 2 8 RPN_CAP 3 1 Bit Range Default & Access 31:24 0h RO Reserved (RSVD): Reserved.
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MCHBAR Registers 7.81 SSKPD—Offset 5D10h This register holds 64 writable bits with no functionality behind them. It is for the convenience of BIOS and graphics drivers. Access Method Type: MEM (Size: 64 bits) Offset: [B:0, D:0, F:0] + 5D10h Default: 0h 6 3 6 0 5 6 5 2 4 8 4 4 4 0 3 6 3 2 2 8 2 4 2 0 1 6 1 2 4 8 0 SKPD 0000000000000000000000000000000000000000000000000000000000000000 Bit Range Field Name (ID): Description 0h RWS 63:0 7.
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MCHBAR Registers Bit Range Field Name (ID): Description 0h RO 31:4 Reserved (RSVD): Reserved. 3 0h RW1S ENABLE_PCIE_NDA_PG: This bit indicates if PCIE-NDA power-gating is enabled (disabled by default). Hardware looks at this bit after RST_CPL is set and decides whether or not to power-gate the PEG controllers and AFE. If it is asserted and all devices are disabled (post CPL), hardware will power-gate the devices. Note 1: This mode does not survive warm-reset, i.e.
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MCHBAR Registers Bit Range Field Name (ID): Description 0h RO 31:4 Reserved (RSVD): Reserved. REQ_DATA: These 4 bits are the data for the request. The only possible request type is MC frequency request. The encoding of this field is the 133/266 MHz multiplier for DCLK/QCLK: Binary Dec DCLK Equation DCLK Freq QCLK Equation QCLK Freq 000b 0d -----------------------------MC PLL – shutdown-------------------------------… 0011b 3d 3*133.33 400.00 MHz 3*266.67 MHz 800.00 MHz 0100b 4d 4*133.33 533.
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MCHBAR Registers 7.85 CONFIG—Offset 5F40h Level 1 configurable TDP settings Access Method Type: MEM (Size: 64 bits) Offset: [B:0, D:0, F:0] + 5F40h Default: 0h 6 3 6 0 5 6 5 2 4 8 4 4 4 0 3 6 3 2 2 8 2 4 2 0 1 6 1 2 8 4 0 Bit Range 63 62:48 47 PKG_TDP 0h RO Reserved (RSVD): Reserved. 0h RO_V PKG_MIN_PWR: Min pkg power setting allowed for this config TDP level. Lower values will be clamped up to this value. Units defined in PACKAGE_POWER_SKU_MSR[PWR_UNIT].
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MCHBAR Registers 7.86 CONFIG—Offset 5F48h Level 2 configurable TDP settings Access Method Type: MEM (Size: 64 bits) Offset: [B:0, D:0, F:0] + 5F48h Default: 0h 6 3 6 0 5 6 5 2 4 8 4 4 4 0 3 6 3 2 2 8 2 4 2 0 1 6 1 2 8 4 0 Bit Range 63 62:48 47 Default & Access 0h RO Reserved (RSVD): Reserved. 0h RO_V PKG_MIN_PWR: Min pkg power setting allowed for this config TDP level 2. Lower values will be clamped up to this value. Units defined in PACKAGE_POWER_SKU_MSR[PWR_UNIT].
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MCHBAR Registers 7.87 CONFIG—Offset 5F50h Rd/Wr register to allow platform SW to select TDP point and set lock Access Method Type: MEM (Size: 32 bits) Offset: [B:0, D:0, F:0] + 5F50h Default: 0h 2 8 0 0 0 0 0 Bit Range 31 30:2 1:0 248 0 0 2 0 0 0 0 0 1 6 0 0 0 0 1 2 0 0 0 0 8 0 0 0 0 RSVD CONFIG_TDP_LOCK 0 2 4 Default & Access 0 0 0 0 0 0 0 0 0 Field Name (ID): Description 0h RWS_KL CONFIG_TDP_LOCK: Config TDP level select lock 0 - unlocked.
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MCHBAR Registers 7.88 TURBO—Offset 5F54h Read/write register to allow MSR/MMIO access to ACPI P-state notify (PCS 33).
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MCHBAR Registers 7.
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MCHBAR Registers Bit Range 7.90 Default & Access Field Name (ID): Description 7 0h RW0C THRESHOLD1_LOG: Sticky log bit that asserts on a 0 to 1 or 1 to 0 transition of the Threshold1_Status bit. HW controls this transition. 6 0h ROV THRESHOLD1_STATUS: Indicates that the current temperature (bits 23:16 in this register) is equal to or higher than the Threshold1 defined in the IA32_PACKAGE_THERM_INTERRUPT MSR.
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MCHBAR Registers Bit Range Default & Access 31:12 0h RO Reserved (RSVD): Reserved. 11 0h RW0C THRESHOLD2_LOG: Sticky log bit that asserts on a 0 to 1 transition of the THRESHOLD2_STATUS bit. HW controls this transition. 10 0h ROV THRESHOLD2_STATUS: Status bit indicating that the hottest DIMM has crossed the THRESHOLD2 value programmed in bits 20:13 of DDR_THERM_DPPM_INTERRUPT. 9 0h RW0C THRESHOLD1_LOG: Sticky log bit that asserts on a 0 to 1 transition of the THRESHOLD1_STATUS bit.
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GFXVTBAR Registers 8 GFXVTBAR Registers Table 8-1.
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GFXVTBAR Registers 8.1 Version Register (VER)—Offset 0h Register to report the architecture version supported. Backward compatibility for the architecture is maintained with new revision numbers, allowing software to load remapping hardware drivers written for prior architecture versions. Access Method Type: MEM (Size: 32 bits) Offset: [B:0, D:0, F:0] + 0h Default: 10h 0 0 0 0 0 2 0 0 0 0 0 1 6 0 0 0 0 1 2 0 0 0 0 8 0 0 0 0 4 0 0 0 Bit Range 8.
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GFXVTBAR Registers Bit Range Default & Access 63:59 0h RO Reserved (RSVD): Reserved. 58 0h RO SL64KP: A value of 1 in this field indicates 64-KByte page size is supported for second-level translation. 57 0h ROV FL64KP: A value of 1 in this field indicates 64-KByte page size is supported for firstlevel translation. 56 1h ROV FL1GP: A value of 1 in this field indicates 1-GByte page size is supported for first-level translation.
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GFXVTBAR Registers Bit Range 21:16 26h RO 15:13 0h RO Field Name (ID): Description MGAW: This field indicates the maximum DMA virtual addressability supported by remapping hardware. The Maximum Guest Address Width (MGAW) is computed as (N+1), where N is the value reported in this field. For example, a hardware implementation supporting 48-bit MGAW reports a value of 47 (101111b) in this field.
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GFXVTBAR Registers Bit Range Field Name (ID): Description 4 0h RO RWBF: 0: Indicates no write-buffer flushing is needed to ensure changes to memory-resident structures are visible to hardware. 1: Indicates software should explicitly flush the write buffers to ensure updates made to memory-resident remapping structures are visible to hardware. 3 0h RO AFL: 0: Indicates advanced fault logging is not supported. Only primary fault logging is supported. 1: Indicates advanced fault logging is supported.
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GFXVTBAR Registers Bit Range 268 Default & Access Field Name (ID): Description 34 1h ROV EAFS: 0: Hardware does not support the extended-accessed (EA) bit in first-level pagingstructure entries. 1: Hardware supports the extendedaccessed (EA) bit in first-level paging-structure entries. This field is valid only when PASID field is reported as Set. 33 1h ROV NWFS: 0: Hardware ignores the "No Write" (NW) flag in Device-TLB translation requests, and behaves as if NW is always 0.
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GFXVTBAR Registers Bit Range 8.4 Default & Access Field Name (ID): Description 4 1h ROV EIM: 0: On Intel®64 platforms, hardware supports only 8-bit APIC-IDs (xAPIC mode). 1: On Intel®64 platforms, hardware supports 32-bit APIC-IDs (x2APIC mode). This field is valid only on Intel®64 platforms reporting Interrupt Remapping support (IR field Set). 3 1h ROV IR: 0: Hardware does not support interrupt remapping. 1: Hardware supports interrupt remapping.
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GFXVTBAR Registers Bit Range 31 30 29 28 27 270 Default & Access Field Name (ID): Description 0h RW_KV TE: Software writes to this field to request hardware to enable/disable DMAremapping: 0: Disable DMA remapping 1: Enable DMA remapping Hardware reports the status of the translation enable operation through the TES field in the Global Status register. There may be active DMA requests in the platform when software updates this field.
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GFXVTBAR Registers Bit Range Default & Access Field Name (ID): Description 0h WO QIE: This field is valid only for implementations supporting queued invalidations. Software writes to this field to enable or disable queued invalidations. 0: Disable queued invalidations. 1: Enable use of queued invalidations. Hardware reports the status of queued invalidation enable operation through QIES field in the Global Status register. The value returned on a read of this field is undefined.
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GFXVTBAR Registers 8.5 Global Status Register (GSTS)—Offset 1Ch Register to report general remapping hardware status.
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GFXVTBAR Registers Bit Range 24 23 22:0 8.6 Default & Access Field Name (ID): Description 0h RO_V IRTPS: This field indicates the status of the interrupt remapping table pointer in hardware. This field is cleared by hardware when software sets the SIRTP field in the Global Command register. This field is Set by hardware when hardware completes the set interrupt remap table pointer operation using the value provided in the Interrupt Remapping Table Address register.
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GFXVTBAR Registers 8.7 Context Command Register (CCMD)—Offset 28h Register to manage context cache. The act of writing the uppermost byte of the CCMD_REG with the ICC field Set causes the hardware to perform the context-cache invalidation.
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GFXVTBAR Registers Bit Range Default & Access Field Name (ID): Description 60:59 1h ROV CAIG: Hardware reports the granularity at which an invalidation request was processed through the CAIG field at the time of reporting invalidation completion (by clearing the ICC field). The following are the encodings for this field: 00: Reserved. 01: Global Invalidation performed. This could be in response to a global, domainselective or device-selective invalidation request.
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GFXVTBAR Registers 8.8 Fault Status Register (FSTS)—Offset 34h Register indicating the various error status. Access Method Type: MEM (Size: 32 bits) Offset: [B:0, D:0, F:0] + 34h Default: 0h 0 0 0 0 0 0 0 0 276 0 0 0 0 0 0 0 FRI 0 0 0 0 0 0 0 0 0 PFO 0 0 PPF 0 4 AFO 0 8 IQE 0 1 2 APF 0 1 6 ITE 0 2 0 ICE 0 2 4 RSVD 0 2 8 PRO 3 1 Bit Range Default & Access 31:16 0h RO Reserved (RSVD): Reserved.
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GFXVTBAR Registers Bit Range Field Name (ID): Description 0h RO AFO: Hardware sets this field to indicate advanced fault log overflow condition. At this time, a fault event is generated based on the programming of the Fault Event Control register. Software writing 1 to this field clears it. Hardware implementations not supporting advanced fault logging implement this bit as RsvdZ. 1 0h ROSV PPF: This field indicates if there are one or more pending faults logged in the fault recording registers.
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GFXVTBAR Registers Bit Range 31 30 29:0 278 Default & Access Field Name (ID): Description 1h RW IM: 0: No masking of interrupt. When an interrupt condition is detected, hardware issues an interrupt message (using the Fault Event Data and Fault Event Address register values). 1: This is the value on reset. Software may mask interrupt message generation by setting this field. Hardware is prohibited from sending the interrupt message when this field is set.
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GFXVTBAR Registers 8.10 Fault Event Data Register (FEDATA)—Offset 3Ch Register specifying the interrupt message data Access Method Type: MEM (Size: 32 bits) Offset: [B:0, D:0, F:0] + 3Ch Default: 0h 0 0 0 2 4 0 0 0 0 2 0 0 0 0 0 1 6 0 0 0 0 1 2 0 0 0 0 8 0 0 0 EIMD 0 2 8 8.11 0 4 0 0 0 0 0 0 0 0 0 IMD 3 1 Bit Range Default & Access 31:16 0h RW EIMD: This field is valid only for implementations supporting 32-bit interrupt data fields.
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GFXVTBAR Registers Bit Range 8.12 Default & Access Field Name (ID): Description 31:2 0h RW MA: When fault events are enabled, the contents of this register specify the DWORDaligned address (bits 31:2) for the interrupt request. 1:0 0h RO Reserved (RSVD): Reserved. Fault Event Upper Address Register (FEUADDR)— Offset 44h Register specifying the interrupt message upper address.
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GFXVTBAR Registers 6 3 6 0 5 6 5 2 4 8 4 4 4 0 3 6 3 2 2 8 2 4 2 0 1 6 1 2 8 4 0 Bit Range 8.14 Default & Access RSVD FLS FLA 0000000000000000000000000000000000000000000000000000000000000000 Field Name (ID): Description 63:12 0h RO FLA: This field specifies the base of 4KB aligned fault-log region in system memory. Hardware ignores and does not implement bits 63:HAW, where HAW is the host address width.
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GFXVTBAR Registers Bit Range 31 0h RW 30:1 0h RO 0 8.15 Default & Access 0h ROV Field Name (ID): Description EPM: This field controls DMA accesses to the protected low-memory and protected high-memory regions. 0: Protected memory regions are disabled. 1: Protected memory regions are enabled. DMA requests accessing protected memory regions are handled as follows: • When DMA remapping is not enabled, all DMA requests accessing protected memory regions are blocked.
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GFXVTBAR Registers Default: 0h 3 1 0 0 0 2 4 0 0 0 0 2 0 0 0 0 0 1 6 0 0 0 0 1 2 0 0 0 0 8 0 0 8.16 0 0 4 0 0 0 0 0 0 0 0 0 RSVD PLMB 0 2 8 Bit Range Default & Access 31:20 0h RW PLMB: This register specifies the base of protected low-memory region in system memory. 19:0 0h RO Reserved (RSVD): Reserved.
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GFXVTBAR Registers 3 1 0 0 0 2 4 0 0 0 0 2 0 0 0 0 0 1 6 0 0 0 0 1 2 0 0 0 0 8 0 0 8.17 0 0 4 0 0 0 0 0 0 0 0 0 RSVD PLML 0 2 8 Bit Range Default & Access 31:20 0h RW PLML: This register specifies the last host physical address of the DMA-protected lowmemory region in system memory. 19:0 0h RO Reserved (RSVD): Reserved.
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GFXVTBAR Registers 8.18 Bit Range Default & Access 63:39 0h RO Reserved (RSVD): Reserved. 38:20 0h RW PHMB: This register specifies the base of protected (high) memory region in system memory. Hardware ignores, and does not implement, bits 63:HAW, where HAW is the host address width. 19:0 0h RO Reserved (RSVD): Reserved. Field Name (ID): Description Protected High-Memory Limit Register (PHMLIMIT)—Offset 78h Register to set up the limit address of DMA-protected high-memory region.
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GFXVTBAR Registers 8.19 Bit Range Default & Access 63:39 0h RO Reserved (RSVD): Reserved. 38:20 0h RW PHML: This register specifies the last host physical address of the DMA-protected high-memory region in system memory. Hardware ignores and does not implement bits 63:HAW, where HAW is the host address width. 19:0 0h RO Reserved (RSVD): Reserved. Field Name (ID): Description Invalidation Queue Head Register (IQH)—Offset 80h Register indicating the invalidation queue head.
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GFXVTBAR Registers 8.20 Invalidation Queue Tail Register (IQT)—Offset 88h Register indicating the invalidation tail head. This register is treated as RsvdZ by implementations reporting Queued Invalidation (QI) as not supported in the Extended Capability register.
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GFXVTBAR Registers 8.21 Invalidation Queue Address Register (IQA)— Offset 90h Register to configure the base address and size of the invalidation queue. This register is treated as RsvdZ by implementations reporting Queued Invalidation (QI) as not supported in the Extended Capability register.
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GFXVTBAR Registers 8.22 Invalidation Completion Status Register (ICS)— Offset 9Ch Register to report completion status of invalidation wait descriptor with Interrupt Flag (IF) Set. This register is treated as RsvdZ by implementations reporting Queued Invalidation (QI) as not supported in the Extended Capability register.
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GFXVTBAR Registers 8.23 Invalidation Event Control Register (IECTL)— Offset A0h Register specifying the invalidation event interrupt control bits. This register is treated as RsvdZ by implementations reporting Queued Invalidation (QI) as not supported in the Extended Capability register.
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GFXVTBAR Registers 8.24 Invalidation Event Data Register (IEDATA)— Offset A4h Register specifying the Invalidation Event interrupt message data. This register is treated as RsvdZ by implementations reporting Queued Invalidation (QI) as not supported in the Extended Capability register. Access Method Type: MEM (Size: 32 bits) Offset: [B:0, D:0, F:0] + A4h Default: 0h 0 0 0 2 4 0 0 0 0 2 0 0 0 0 0 1 6 0 0 0 0 1 2 0 0 0 0 8 0 0 EIMD 0 2 8 8.
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GFXVTBAR Registers 3 1 0 0 0 2 4 0 0 0 0 2 0 0 0 0 0 1 6 0 0 0 0 1 2 0 0 0 0 8 0 0 0 0 4 0 0 0 0 0 0 0 Bit Range 31:2 1:0 8.26 Default & Access 0 0 RSVD MA 0 2 8 Field Name (ID): Description 0h RW_L MA: When fault events are enabled, the contents of this register specify the DWORDaligned address (bits 31:2) for the interrupt request. 0h RO Reserved (RSVD): Reserved.
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GFXVTBAR Registers 8.27 Interrupt Remapping Table Address Register (IRTA)—Offset B8h Register providing the base address of Interrupt remapping table. This register is treated as RsvdZ by implementations reporting Interrupt Remapping (IR) as not supported in the Extended Capability register.
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GFXVTBAR Registers 8.28 Fault Recording Low Register (FRCDL)—Offset 400h Register to record fault information when primary fault logging is active. Hardware reports the number and location of fault recording registers through the Capability register. This register is relevant only for primary fault logging. This register is sticky and can be cleared only through power good reset or by software clearing the RW1C fields by writing a 1.
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GFXVTBAR Registers 6 3 6 0 5 6 5 2 4 8 4 4 4 0 3 6 3 2 2 8 2 4 2 0 1 6 1 2 8 4 0 Bit Range Default & Access SID RSVD PP EXE PRIV FR PN F T AT 0000000000000000000000000000000000000000000000000000000000000000 Field Name (ID): Description 0h RW1CS F: Hardware sets this field to indicate a fault is logged in this Fault Recording register. The F field is set by hardware after the details of the fault is recorded in other fields.
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GFXVTBAR Registers 8.30 Invalidate Address Register (IVA)—Offset 500h Register to provide the DMA address whose corresponding IOTLB entry needs to be invalidated through the corresponding IOTLB Invalidate register. This register is a write-only register. Access Method Type: MEM (Size: 64 bits) Offset: [B:0, D:0, F:0] + 500h Default: 0h 6 3 6 0 5 6 5 2 4 8 4 4 4 0 3 6 3 2 2 8 2 4 2 0 1 6 1 2 4 8 0 AM IH RSVD Bit Range Default & Access 63:39 0h RO Reserved (RSVD): Reserved.
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GFXVTBAR Registers 8.31 IOTLB Invalidate Register (IOTLB)—Offset 508h Register to invalidate IOTLB. The act of writing the upper byte of the IOTLB_REG with IVT field Set causes the hardware to perform the IOTLB invalidation.
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GFXVTBAR Registers Bit Range Field Name (ID): Description 58:57 1h ROV IAIG: Hardware reports the granularity at which an invalidation request was processed through this field when reporting invalidation completion (by clearing the IVT field). The following are the encodings for this field. 00: Reserved. This indicates hardware detected an incorrect invalidation request and ignored the request.
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GFXVTBAR Registers 8.32 DMA Remap Engine Policy Control (ARCHDIS)— Offset FF0h This register contains all architectural disables and defeatures for the graphics DMA remap engine.
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GFXVTBAR Registers Bit Range Field Name (ID): Description 11 0h RW_L DTCAPDIS: This bit allows hiding the Device TLB Capability. 0: ECAP_REG[DT] is determined by its own default value. 1: ECAP_REG[DT] is set to 0b. 10 0h RW_L PASIDCAPDIS: This bit allows hiding the PASID Capability. 0: ECAP_REG[PASID] is determined by its own default value. 1: ECAP_REG[PASID] is set to 0b. 9 0h RW_L ECSCAPDIS: This bit allows hiding the Extended Context Capability.
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GFXVTBAR Registers 8.33 DMA Remap Engine Policy Control (UARCHDIS)— Offset FF4h This register contains all micro-architectural disables and defeatures for the graphics DMA remap engine.
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GFXVTBAR Registers Bit Range Default & Access Field Name (ID): Description 13 0h RW_L L1DIS: 1: L1 TLB is disabled, and each GPA request that looks up the L1 will result in a miss. 0: Normal mode (default). L1 is enabled. 12 0h RW_L L0DIS: 1: L0 TLB is disabled, and each GPA request that looks up the L0 will result in a miss. 0: Normal mode (default). L0 is enabled. 11 0h RW_L CCDIS: 1: Context Cache is disabled. Each GPA request results in a miss and will request a root walk.
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PXPEPBAR Registers 9 PXPEPBAR Registers Table 9-1. Summary of Bus: 0, Device: 0, Function: 0 (MEM) Size (Bytes) Offset 14–17h 9.1 Default Value Register Name (Register Symbol) 4 EP VC 0 Resource Control (EPVC0RCTL)—Offset 14h 800000FFh EP VC 0 Resource Control (EPVC0RCTL)—Offset 14h Controls the resources associated with Egress Port Virtual Channel 0.
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PXPEPBAR Registers Bit Range Default & Access 16:8 0h RO Reserved (RSVD): Reserved. 7:1 7Fh RW TCVC0M: TC/VC0 Map: Indicates the TCs (Traffic Classes) that are mapped to the VC resource. Bit locations within this field correspond to TC values. For example, when bit 7 is set in this field, TC7 is mapped to this VC resource. When more than one bit in this field is set, it indicates that multiple TCs are mapped to the VC resource.
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VC0PREMAP Registers 10 VC0PREMAP Registers Table 10-1.
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VC0PREMAP Registers 10.1 Version Register (VER)—Offset 0h Register to report the architecture version supported. Backward compatibility for the architecture is maintained with new revision numbers, allowing software to load remapping hardware drivers written for prior architecture versions. Access Method Type: MEM (Size: 32 bits) Offset: [B:0, D:0, F:0] + 0h Default: 10h 0 0 0 0 0 0 2 0 0 0 0 1 6 0 0 0 0 0 1 2 0 0 0 0 8 0 0 0 0 4 0 0 Bit Range 10.
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VC0PREMAP Registers Bit Range Default & Access 63:59 0h RO Reserved (RSVD): Reserved. 58 0h RO SL64KP: A value of 1 in this field indicates 64-KByte page size is supported for second-level translation. 57 0h RO FL64KP: A value of 1 in this field indicates 64-KByte page size is supported for firstlevel translation. 56 0h RO FL1GP: A value of 1 in this field indicates 1-GByte page size is supported for first-level translation.
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VC0PREMAP Registers Bit Range Field Name (ID): Description 21:16 26h RO MGAW: This field indicates the maximum DMA virtual addressability supported by remapping hardware. The Maximum Guest Address Width (MGAW) is computed as (N+1), where N is the value reported in this field. For example, a hardware implementation supporting 48-bit MGAW reports a value of 47 (101111b) in this field.
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VC0PREMAP Registers 10.
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VC0PREMAP Registers Bit Range 310 Default & Access Field Name (ID): Description 28 0h RO PASID: 0: Hardware does not support process address space IDs. 1: Hardware supports Process Address Space IDs. 27 0h RO DIS: 0: Hardware does not support deferred invalidations of IOTLB and Device-TLB. 1: Hardware supports deferred invalidations of IOTLB and Device-TLB. 26 0h RO NEST: 0: Hardware does not support nested translations. 1: Hardware supports nested translations.
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VC0PREMAP Registers Bit Range 10.4 Default & Access Field Name (ID): Description 2 0h RO DT: 0: Hardware does not support device-IOTLBs. 1: Hardware supports Device-IOTLBs. Implementations reporting this field as Set should also support Queued Invalidation (QI). 1 1h ROV QI: 0: Hardware does not support queued invalidations. 1: Hardware supports queued invalidations.
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VC0PREMAP Registers Bit Range 31 30 29 28 27 312 Default & Access Field Name (ID): Description 0h WO TE: Software writes to this field to request hardware to enable/disable DMAremapping: 0: Disable DMA remapping 1: Enable DMA remapping Hardware reports the status of the translation enable operation through the TES field in the Global Status register. There may be active DMA requests in the platform when software updates this field.
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VC0PREMAP Registers Bit Range Default & Access Field Name (ID): Description 0h WO QIE: This field is valid only for implementations supporting queued invalidations. Software writes to this field to enable or disable queued invalidations. 0: Disable queued invalidations. 1: Enable use of queued invalidations. Hardware reports the status of queued invalidation enable operation through QIES field in the Global Status register. The value returned on a read of this field is undefined.
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VC0PREMAP Registers 10.5 Global Status Register (GSTS)—Offset 1Ch Register to report general remapping hardware status.
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VC0PREMAP Registers Bit Range 24 23 22:0 10.6 Default & Access Field Name (ID): Description 0h RO_V IRTPS: This field indicates the status of the interrupt remapping table pointer in hardware. This field is cleared by hardware when software sets the SIRTP field in the Global Command register. This field is Set by hardware when hardware completes the set interrupt remap table pointer operation using the value provided in the Interrupt Remapping Table Address register.
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VC0PREMAP Registers 10.7 Context Command Register (CCMD)—Offset 28h Register to manage context cache. The act of writing the uppermost byte of the CCMD_REG with the ICC field Set causes the hardware to perform the context-cache invalidation.
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VC0PREMAP Registers Bit Range Default & Access Field Name (ID): Description 60:59 0h ROV CAIG: Hardware reports the granularity at which an invalidation request was processed through the CAIG field at the time of reporting invalidation completion (by clearing the ICC field). The following are the encodings for this field: 00: Reserved. 01: Global Invalidation performed. This could be in response to a global, domainselective or device-selective invalidation request.
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VC0PREMAP Registers 10.8 Fault Status Register (FSTS)—Offset 34h Register indicating the various error status. Access Method Type: MEM (Size: 32 bits) Offset: [B:0, D:0, F:0] + 34h Default: 0h 0 0 0 0 0 0 0 0 318 0 0 0 0 0 0 0 FRI 0 0 0 0 0 0 0 0 0 PFO 0 0 PPF 0 4 AFO 0 8 IQE 0 1 2 APF 0 1 6 ITE 0 2 0 ICE 0 2 4 RSVD 0 2 8 PRO 3 1 Bit Range Default & Access 31:16 0h RO Reserved (RSVD): Reserved.
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VC0PREMAP Registers Bit Range Field Name (ID): Description 0h RO AFO: Hardware sets this field to indicate advanced fault log overflow condition. At this time, a fault event is generated based on the programming of the Fault Event Control register. Software writing 1 to this field clears it. Hardware implementations not supporting advanced fault logging implement this bit as RsvdZ. 1 0h ROSV PPF: This field indicates if there are one or more pending faults logged in the fault recording registers.
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VC0PREMAP Registers Bit Range 31 30 29:0 320 Default & Access Field Name (ID): Description 1h RW IM: 0: No masking of interrupt. When an interrupt condition is detected, hardware issues an interrupt message (using the Fault Event Data and Fault Event Address register values). 1: This is the value on reset. Software may mask interrupt message generation by setting this field. Hardware is prohibited from sending the interrupt message when this field is set.
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VC0PREMAP Registers 10.10 Fault Event Data Register (FEDATA)—Offset 3Ch Register specifying the interrupt message data Access Method Type: MEM (Size: 32 bits) Offset: [B:0, D:0, F:0] + 3Ch Default: 0h 0 0 0 2 4 0 0 0 0 2 0 0 0 0 0 1 6 0 0 0 0 1 2 0 0 0 0 8 0 0 0 EIMD 0 2 8 10.11 0 4 0 0 0 0 0 0 0 0 0 IMD 3 1 Bit Range Default & Access 31:16 0h RW EIMD: This field is valid only for implementations supporting 32-bit interrupt data fields.
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VC0PREMAP Registers Bit Range 10.12 Default & Access Field Name (ID): Description 31:2 0h RW MA: When fault events are enabled, the contents of this register specify the DWORDaligned address (bits 31:2) for the interrupt request. 1:0 0h RO Reserved (RSVD): Reserved. Fault Event Upper Address Register (FEUADDR)— Offset 44h Register specifying the interrupt message upper address.
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VC0PREMAP Registers 6 3 6 0 5 6 5 2 4 8 4 4 4 0 3 6 3 2 2 8 2 4 2 0 1 6 1 2 8 4 0 Bit Range 10.14 Default & Access RSVD FLS FLA 0000000000000000000000000000000000000000000000000000000000000000 Field Name (ID): Description 63:12 0h RO FLA: This field specifies the base of 4KB aligned fault-log region in system memory. Hardware ignores and does not implement bits 63:HAW, where HAW is the host address width.
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VC0PREMAP Registers Bit Range 31 0h RW 30:1 0h RO 0 10.15 Default & Access 0h ROV Field Name (ID): Description EPM: This field controls DMA accesses to the protected low-memory and protected high-memory regions. 0: Protected memory regions are disabled. 1: Protected memory regions are enabled. DMA requests accessing protected memory regions are handled as follows: • When DMA remapping is not enabled, all DMA requests accessing protected memory regions are blocked.
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VC0PREMAP Registers Default: 0h 3 1 0 0 0 2 4 0 0 0 0 2 0 0 0 0 0 1 6 0 0 0 0 10.16 1 2 0 0 0 0 8 0 0 0 0 4 0 0 0 0 0 0 0 0 0 RSVD PLMB 0 2 8 Bit Range Default & Access 31:20 0h RW PLMB: This register specifies the base of protected low-memory region in system memory. 19:0 0h RO Reserved (RSVD): Reserved.
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VC0PREMAP Registers Access Method Type: MEM (Size: 32 bits) Offset: [B:0, D:0, F:0] + 6Ch Default: 0h 3 1 0 0 0 2 4 0 0 0 0 2 0 0 0 0 0 1 6 0 0 0 0 1 2 0 0 0 0 8 0 0 10.17 0 0 4 0 0 0 0 0 0 0 0 0 RSVD PLML 0 2 8 Bit Range Default & Access 31:20 0h RW PLML: This register specifies the last host physical address of the DMA-protected lowmemory region in system memory. 19:0 0h RO Reserved (RSVD): Reserved.
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VC0PREMAP Registers 6 3 6 0 5 6 5 2 4 8 4 4 4 0 3 6 3 2 2 8 2 4 2 0 1 6 1 2 8 4 0 10.18 RSVD RSVD PHMB 0000000000000000000000000000000000000000000000000000000000000000 Bit Range Default & Access 63:39 0h RO Reserved (RSVD): Reserved. 38:20 0h RW PHMB: This register specifies the base of protected (high) memory region in system memory. Hardware ignores, and does not implement, bits 63:HAW, where HAW is the host address width. 19:0 0h RO Reserved (RSVD): Reserved.
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VC0PREMAP Registers 6 3 6 0 5 6 5 2 4 8 4 4 4 0 3 6 3 2 2 8 2 4 2 0 1 6 1 2 8 4 0 10.19 RSVD PHML RSVD 0000000000000000000000000000000000000000000000000000000000000000 Bit Range Default & Access 63:39 0h RO Reserved (RSVD): Reserved. 38:20 0h RW PHML: This register specifies the last host physical address of the DMA-protected high-memory region in system memory. Hardware ignores and does not implement bits 63:HAW, where HAW is the host address width.
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VC0PREMAP Registers Bit Range Default & Access 63:19 0h RO Reserved (RSVD): Reserved. 0h ROV QH: Specifies the offset (128-bit aligned) to the invalidation queue for the command that will be fetched next by hardware. Hardware resets this field to 0 whenever the queued invalidation is disabled (QIES field Clear in the Global Status register). 0h RO Reserved (RSVD): Reserved. 18:4 3:0 10.
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VC0PREMAP Registers 10.21 Invalidation Queue Address Register (IQA)— Offset 90h Register to configure the base address and size of the invalidation queue. This register is treated as RsvdZ by implementations reporting Queued Invalidation (QI) as not supported in the Extended Capability register.
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VC0PREMAP Registers 3 1 2 8 0 0 0 0 0 0 0 2 0 0 0 0 0 1 6 0 0 0 0 1 2 0 0 0 0 8 0 0 0 0 4 0 0 0 0 0 0 0 0 Bit Range 31:1 0 10.23 Default & Access 0 IWC RSVD 0 2 4 Field Name (ID): Description 0h RO Reserved (RSVD): Reserved. 0h RW1CS IWC: Indicates completion of Invalidation Wait Descriptor with Interrupt Flag (IF) field Set. Hardware implementations not supporting queued invalidations implement this field as RsvdZ.
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VC0PREMAP Registers Bit Range 31 30 29:0 10.24 Default & Access Field Name (ID): Description 1h RW_L IM: 0: No masking of interrupt. When a invalidation event condition is detected, hardware issues an interrupt message (using the Invalidation Event Data & Invalidation Event Address register values). 1: This is the value on reset. Software may mask interrupt message generation by setting this field. Hardware is prohibited from sending the interrupt message when this field is Set.
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VC0PREMAP Registers 10.25 Bit Range Default & Access 31:16 0h RW_L EIMD: This field is valid only for implementations supporting 32-bit interrupt data fields. Hardware implementations supporting only 16-bit interrupt data treat this field as Rsvd. 15:0 0h RW_L IMD: Data value in the interrupt request. Field Name (ID): Description Invalidation Event Address Register (IEADDR)— Offset A8h Register specifying the Invalidation Event Interrupt message address.
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VC0PREMAP Registers 10.26 Invalidation Event Upper Address Register (IEUADDR)—Offset ACh Register specifying the Invalidation Event interrupt message upper address. Access Method Type: MEM (Size: 32 bits) Offset: [B:0, D:0, F:0] + ACh Default: 0h 3 1 0 0 2 4 0 0 0 0 2 0 0 0 0 0 1 6 0 0 0 0 1 2 0 0 0 0 8 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 MUA 0 2 8 Bit Range 31:0 10.
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VC0PREMAP Registers Bit Range Default & Access 63:39 0h RO Reserved (RSVD): Reserved. 38:12 0h RW_L IRTA: This field points to the base of 4KB aligned interrupt remapping table. Hardware ignores and does not implement bits 63:HAW, where HAW is the host address width. Reads of this field returns value that was last programmed to it. 0h ROV EIME: This field is used by hardware on Intel®64 platforms as follows: 0: xAPIC mode is active.
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VC0PREMAP Registers Bit Range 63:12 11:0 10.29 Default & Access Field Name (ID): Description 0h ROSV FI: When the Fault Reason (FR) field indicates one of the DMA-remapping fault conditions, bits 63:12 of this field contain the page address in the faulted DMA request. Hardware treats bits 63:N as reserved (0), where N is the maximum guest address width (MGAW) supported.
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VC0PREMAP Registers Bit Range Default & Access 59:40 0h RO PN: PASID value in the faulted request. This field is relevant only when the PP field is set. Hardware implementations not supporting PASID (PASID field Clear in Extended Capability register) implement this field as RsvdZ. 39:32 0h ROSV FR: Reason for the fault. This field is relevant only when the F field is set. 31 0h RO PP: When set, indicates the faulted request has a PASID tag.
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VC0PREMAP Registers Bit Range Default & Access 63:39 0h RO Reserved (RSVD): Reserved. 38:12 0h RW ADDR: Software provides the DMA address that needs to be page-selectively invalidated. To make a page-selective invalidation request to hardware, software should first write the appropriate fields in this register, and then issue the appropriate page-selective invalidate command through the IOTLB_REG. Hardware ignores bits 63 : N, where N is the maximum guest address width (MGAW) supported.
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VC0PREMAP Registers Bit Range Default & Access 63 0h RW_V 62 0h RO Field Name (ID): Description IVT: Software requests IOTLB invalidation by setting this field. Software should also set the requested invalidation granularity by programming the IIRG field. Hardware clears the IVT field to indicate the invalidation request is complete. Hardware also indicates the granularity at which the invalidation operation was performed through the IAIG field.
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VC0PREMAP Registers Bit Range Default & Access 47:40 0h RO Field Name (ID): Description Reserved (RSVD): Reserved. 39:32 0h RW DID: Indicates the ID of the domain whose IOTLB entries need to be selectively invalidated. This field should be programmed by software for domain-selective and page-selective invalidation requests. The Capability register reports the domain-id width supported by hardware. Software should ensure that the value written to this field is within this limit.
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IMGU Registers 11 IMGU Registers Table 11-1.
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IMGU Registers 11.1 Vendor Identification (VID)—Offset 0h This register combined with the Device Identification register uniquely identify any PCI device. Access Method Type: CFG (Size: 16 bits) Offset: [B:0, D:5, F:0] + 0h Default: 8086h 15 0 0 0 8 0 0 0 4 0 1 0 0 0 0 0 1 1 0 VID 1 12 Bit Range Default & Access 8086h RO 15:0 11.2 Field Name (ID): Description VID: PCI standard identification for Intel.
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IMGU Registers 11.3 PCI Command (PCICMD)—Offset 4h This 16-bit register provides basic control over the IMGU device's ability to respond to PCI cycles. The PCICMD Register in the IMGU disables the IMGU PCI compliant master accesses to main memory.
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IMGU Registers 11.4 PCI Status (PCISTS)—Offset 6h This register reports the status of the IMGU. Access Method Type: CFG (Size: 16 bits) Offset: [B:0, D:5, F:0] + 6h Default: 10h Default & Access 0 0 0 1 0 CAP66 CLIST IS 0 0 0 RSVD 0 RSVD 0 0 FB2B 0 4 DPD 0 DEVT 0 STAS SSE 0 RCAS 0 8 RURS 0 Bit Range Field Name (ID): Description 15 0h RO DPE: The IMGU does not implement this bit and it is hardwired to a 0. Writes to this bit position have no effect.
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IMGU Registers 11.5 Revision Identification and Class Code (RID)— Offset 8h This is an 8-bit value that indicates the revision identification number for the device. Access Method Type: CFG (Size: 32 bits) Offset: [B:0, D:5, F:0] + 8h Default: 4800001h 0 0 0 1 0 0 2 0 1 0 0 0 0 0 0 0 0 0 SUBCC 0 1 2 0 8 0 0 0 0 4 0 0 0 0 0 0 0 0 Bit Range Default & Access 31:24 4h RW_O BCC: Indicates the base class code for this device.
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IMGU Registers Bit Range 7:0 11.7 Default & Access Field Name (ID): Description CLS: This field is hardwired to 0. The IMGU as a PCI compliant master does not use the Memory Write and Invalidate command and, in general, does not perform operations based on cache line size. 0h RO Master Latency Timer (MLT)—Offset Dh The IMGU Device does not support the programmability of the master latency timer because it does not perform bursts.
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IMGU Registers Bit Range 7:0 11.9 Default & Access 0h RO Field Name (ID): Description HDR: This field always returns 0 to indicate that the IMGU device is a single function device with standard header layout. Built In Self Test (BIST)—Offset Fh This register is used for control and status of Built In Self Test (BIST). Access Method Type: CFG (Size: 8 bits) Offset: [B:0, D:5, F:0] + Fh Default: 0h 7 4 0 0 0 0 0 0 0 0 BIST 0 Bit Range 7:0 11.
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IMGU Registers 11.11 Bit Range Default & Access 63:39 0h RW RSVDRW: should be set to 0 since addressing above 512GB is not supported. 38:22 0h RW IMGBA: This field corresponds to bits 38 to 22 of the base address IMGUBAR address space. BIOS will program this register resulting in a base address for a 4MB block of contiguous memory address space. This register ensures that a naturally aligned 4MB space is allocated within total addressable memory space.
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IMGU Registers 11.12 Subsystem Identification (SID)—Offset 2Eh This value is used to identify a particular subsystem. Access Method Type: CFG (Size: 16 bits) Offset: [B:0, D:5, F:0] + 2Eh Default: 0h 15 12 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 SUBID 0 8 Bit Range 15:0 11.13 Default & Access 0h RW_O Field Name (ID): Description SUBID: This field should be programmed during BIOS initialization. After it has been written once, it becomes read only.
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IMGU Registers 11.14 Interrupt Line (INTRLINE)—Offset 3Ch Access Method Type: CFG (Size: 8 bits) Offset: [B:0, D:5, F:0] + 3Ch Default: 0h 7 4 0 0 0 0 0 0 0 INTCON 0 0 Bit Range 7:0 11.15 Default & Access Field Name (ID): Description INTCON: Used to communicate interrupt line routing information. BIOS Requirement: POST software writes the routing information into this register as it initializes and configures the system.
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IMGU Registers 11.16 Message Signaled Interrupts Capability ID (MSI)—Offset 90h When a device supports MSI it can generate an interrupt request to the processor by writing a predefined data item (a message) to a predefined memory address. The reporting of the existence of this capability can be disabled by setting MSICH (CAPL[0] @ 7Fh). In that case walking this linked list will skip this capability and instead go directly to the PCI PM capability.
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IMGU Registers Bit Range 11.18 Default & Access Field Name (ID): Description 15:8 0h RO Reserved (RSVD): Reserved. 7 1h RO AC64: Hardwired to 0 to indicate that the function does not implement the upper 32 bits of the Message Address register and is incapable of generating a 64-bit memory address. This may need to change in future implementations when addressable system memory exceeds the 32bit/4GB limit. 6:4 0h RO MME: Multiple Message Enable (MME): Normally this is a RW register.
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IMGU Registers 11.19 Message Address (MA)—Offset 98h Access Method Type: CFG (Size: 32 bits) Offset: [B:0, D:5, F:0] + 98h Default: 0h 3 1 2 8 0 0 0 0 0 0 0 2 0 0 0 0 0 1 6 0 0 0 0 1 2 0 0 0 0 8 0 0 0 0 4 0 0 0 0 0 0 0 0 0 MA 0 2 4 Bit Range Default & Access 11.20 MA: Used by system software to assign an MSI address to the device. The device handles an MSI by writing the padded contents of the MD register to this address.
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IMGU Registers 11.21 Advanced Features Capabilities - ID and Next Pointer (AFCIDNP)—Offset A0h This RO register holds part of the Advanced Features Capabilities - ID and Next-Pointer Access Method Type: CFG (Size: 16 bits) Offset: [B:0, D:5, F:0] + A0h Default: D013h 12 1 0 8 1 0 0 0 0 4 0 0 0 Bit Range 11.
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IMGU Registers 11.23 Bit Range Default & Access 15:10 0h RO Reserved (RSVD): Reserved.
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IMGU Registers 11.24 Advanced Features Status (AFSTS)—Offset A5h Access Method Type: CFG (Size: 8 bits) Offset: [B:0, D:5, F:0] + A5h Default: 0h 7 4 0 0 0 0 0 0 0 Bit Range 7:1 0 11.25 TP RSVD 0 0 Default & Access Field Name (ID): Description 0h RO Reserved (RSVD): Reserved. 0h ROV TP: Transactions Pending: 1: The Function has issued one or more non-posted transactions which have not been completed, including non-posted transactions that a target has terminated with Retry.
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IMGU Registers Bit Range Default & Access 31:24 0h RO DT: Does not apply. Hardwired to 0 23 0h RO BPCCE: Does not apply. Hardwired to 0 22 0h RO B23: This bit is hardwired to 0 21:16 0h RO Reserved (RSVD): Reserved. 15 0h RO PMES: This bit is hardwired to 0 to indicate that PME# assertion from D3 (cold) is disabled. 14:13 0h RO DS: These bits are hardwired to zero. The IMGU does not support data register. 12:9 0h RO DSEL: These bits are hardwired to zero.
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PCI Express* Controller (x16) Registers 12 PCI Express* Controller (x16) Registers Table 12-1.
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PCI Express* Controller (x16) Registers Table 12-1.
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PCI Express* Controller (x16) Registers 12.1 Vendor Identification (VID)—Offset 0h This register combined with the Device Identification register uniquely identify any PCI device. Access Method Type: CFG (Size: 16 bits) Offset: [B:0, D:1, F:0] + 0h Default: 8086h 15 12 0 0 0 8 0 0 0 4 0 1 0 0 0 0 0 1 1 0 VID 1 Bit Range Default & Access 8086h RO 15:0 12.2 Field Name (ID): Description VID: Vendor Identification: PCI standard identification for Intel.
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PCI Express* Controller (x16) Registers 12.3 PCI Command (PCICMD)—Offset 4h Access Method Type: CFG (Size: 16 bits) Offset: [B:0, D:1, F:0] + 4h Default: 0h 0 0 0 0 0 0 0 0 0 0 0 PERRE VGAPS MWIE SCE BME MAE IOAE 0 0 RSVD 0 4 SERRE 0 8 FB2B 0 RSVD 0 12 INTAAD 15 Bit Range Default & Access 15:11 0h RO Reserved (RSVD): Reserved. 0h RW INTAAD: INTA Assertion Disable: 0: This device is permitted to generate INTA interrupt messages.
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PCI Express* Controller (x16) Registers Bit Range Default & Access 0h RW BME: Bus Master Enable: Bus Master Enable (BME): Controls the ability of the PEG port to forward Memory Read/Write Requests in the upstream direction. 0: This device is prevented from making memory requests to its primary bus.
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PCI Express* Controller (x16) Registers Bit Range Default & Access Field Name (ID): Description 0h RW1C DPE: Detected Parity Error: This bit is Set by a Function whenever it receives a Poisoned TLP, regardless of the state the Parity Error Response bit in the Command register. On a Function with a Type 1 Configuration header, the bit is Set when the Poisoned TLP is received by its Primary Side. Default value of this bit is 0b.
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PCI Express* Controller (x16) Registers Bit Range 4 Default & Access 1h RO CAPL: Capabilities List: Indicates that a capabilities list is present. Hardwired to 1. 0h ROV INTAS: INTx Status: Indicates that an interrupt message is pending internally to the device. Only PME and Hot Plug sources feed into this status bit (not PCI INTA-INTD assert and de-assert messages). The INTA Assertion Disable bit, PCICMD1[10], has no effect on this bit.
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PCI Express* Controller (x16) Registers 0 0 1 6 0 0 1 1 0 1 2 0 0 0 12.7 8 0 0 1 0 0 4 0 0 0 0 0 SUBCC BCC 0 2 0 0 0 0 0 PI 2 3 Bit Range Default & Access 23:16 6h RO BCC: Base Class Code: Indicates the base class code for this device. This code has the value 06h, indicating a Bridge device. 15:8 4h RO SUBCC: Sub-Class Code: Indicates the sub-class code for this device. The code is 04h indicating a PCI to PCI Bridge.
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PCI Express* Controller (x16) Registers 7 4 0 0 0 0 0 0 0 1 HDR 1 Bit Range 7:0 12.9 Default & Access 81h RO Field Name (ID): Description HDR: Header Type Register: Device #1 returns 81 to indicate that this is a multi function device with bridge header layout. Device #6 returns 01 to indicate that this is a single function device with bridge header layout. Primary Bus Number (PBUSN)—Offset 18h This register identifies that this "virtual" Host-PCI Express bridge is connected to PCI bus #0.
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PCI Express* Controller (x16) Registers 7 4 0 0 0 0 0 0 0 0 BUSN 0 Bit Range 7:0 12.11 Default & Access 0h RW Field Name (ID): Description BUSN: Secondary Bus Number: This field is programmed by configuration software with the bus number assigned to PCI Express-G. Subordinate Bus Number (SUBUSN)—Offset 1Ah This register identifies the subordinate bus (if any) that resides at the level below PCI Express-G.
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PCI Express* Controller (x16) Registers 12.12 I/O Base Address (IOBASE)—Offset 1Ch This register controls the Processor to PCI Express-G I/O access routing based on the following formula: IO_BASE=< address =<IO_LIMIT Only upper 4 bits are programmable. For the purpose of address decode address bits A[11:0] are treated as 0. Thus the bottom of the defined I/O address range will be aligned to a 4KB boundary.
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PCI Express* Controller (x16) Registers 7 4 0 0 0 0 0 0 0 Bit Range 12.14 0 RSVD IOLIMIT 0 Default & Access Field Name (ID): Description 7:4 0h RW IOLIMIT: I/O Address Limit: Corresponds to A[15:12] of the I/O address limit of the root port. Devices between this upper limit and IOBASE1 will be passed to the PCI Express hierarchy associated with this device. 3:0 0h RO Reserved (RSVD): Reserved.
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PCI Express* Controller (x16) Registers Bit Range Default & Access 0h RO DEVT: DEVSELB Timing: Not Applicable or Implemented. Hardwired to 0. 8 0h RW1C SMDPE: Master Data Parity Error: When set indicates that the Processor received across the link (upstream) a Read Data Completion Poisoned TLP (EP=1). This bit can only be set when the Parity Error Enable bit in the Bridge Control register is set. 7 0h RO FB2B: Fast Back-to-Back: Not Applicable or Implemented. Hardwired to 0.
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PCI Express* Controller (x16) Registers 12.16 Memory Limit Address (MLIMIT)—Offset 22h This register controls the Processor to PCI Express-G non-prefetchable memory access routing based on the following formula: MEMORY_BASE=< address =<MEMORY_LIMIT The upper 12 bits of the register are read/write and correspond to the upper 12 address bits A[31:20] of the 32 bit address. The bottom 4 bits of this register are readonly and return zeros when read.
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PCI Express* Controller (x16) Registers 12.17 Prefetchable Memory Base Address (PMBASE)— Offset 24h This register in conjunction with the corresponding Upper Base Address register controls the Processor to PCI Express-G prefetchable memory access routing based on the following formula: PREFETCHABLE_MEMORY_BASE =< address =< PREFETCHABLE_MEMORY_LIMIT The upper 12 bits of this register are read/write and correspond to address bits A[31:20] of the 40-bit address.
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PCI Express* Controller (x16) Registers memory range is supported to allow segregation by the configuration software between the memory ranges that should be defined as UC and the ones that can be designated as a USWC (i.e. prefetchable) from the Processor perspective. Access Method Type: CFG (Size: 16 bits) Offset: [B:0, D:1, F:0] + 26h Default: 1h 12 0 0 0 8 0 0 0 0 4 0 0 0 0 0 0 0 PMLIMIT 0 Bit Range 12.
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PCI Express* Controller (x16) Registers 3 1 0 0 0 2 4 0 0 0 0 2 0 0 0 0 0 1 6 0 0 0 0 1 2 0 0 0 0 8 0 0 0 0 4 0 0 0 0 0 0 0 0 0 PMBASEU 0 2 8 Bit Range 31:0 12.20 Default & Access 0h RW Field Name (ID): Description PMBASEU: Prefetchable Memory Base Address: Corresponds to A[63:32] of the lower limit of the prefetchable memory range that will be passed to PCI Express-G.
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PCI Express* Controller (x16) Registers 3 1 0 0 0 2 4 0 0 0 0 2 0 0 0 0 0 1 6 0 0 0 0 1 2 0 0 0 0 8 0 0 0 0 4 0 0 0 0 0 0 0 0 0 PMLIMITU 0 2 8 Bit Range 31:0 12.21 Default & Access 0h RW Field Name (ID): Description PMLIMITU: Prefetchable Memory Address Limit: Corresponds to A[63:32] of the upper limit of the prefetchable Memory range that will be passed to PCI Express-G.
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PCI Express* Controller (x16) Registers Default: 0h 7 4 0 0 0 0 0 0 0 0 INTCON 0 Bit Range 7:0 12.23 Default & Access 0h RW Field Name (ID): Description INTCON: Interrupt Connection: Used to communicate interrupt line routing information. BIOS Requirement: POST software writes the routing information into this register as it initializes and configures the system. The value indicates to which input of the system interrupt controller this device's interrupt pin is connected.
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PCI Express* Controller (x16) Registers 12.24 Bridge Control (BCTRL)—Offset 3Eh This register provides extensions to the PCICMD register that are specific to PCI-PCI bridges. The BCTRL provides additional control for the secondary interface (i.e. PCI Express-G) as well as some bits that affect the overall behavior of the "virtual" HostPCI Express bridge embedded within the CPU, e.g. VGA compatible address ranges mapping.
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PCI Express* Controller (x16) Registers Bit Range Default & Access Field Name (ID): Description 0h RW ISAEN: ISA Enable: Needed to exclude legacy resource decode to route ISA resources to legacy decode path. Modifies the response by the root port to an I/O access issued by the Processor that target ISA I/O addresses. This applies only to I/O addresses that are enabled by the IOBASE and IOLIMIT registers.
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PCI Express* Controller (x16) Registers Bit Range Field Name (ID): Description 21 0h RO DSI: Device Specific Initialization: Hardwired to 0 to indicate that special initialization of this device is NOT required before generic class device driver is to use it. 20 0h RO APS: Auxiliary Power Source: Hardwired to 0. 19 0h RO PMECLK: PME Clock: Hardwired to 0 to indicate this device does NOT support PMEB generation.
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PCI Express* Controller (x16) Registers Bit Range 8 7:4 Default & Access 0h RW PMEE: PME Enable: Indicates that this device does not generate PMEB assertion from any D-state. 0: PMEB generation not possible from any D State 1: PMEB generation enabled from any D State The setting of this bit has no effect on hardware. See PM_CAP[15:11] 0h RO Reserved (RSVD): Reserved. 1h RO NSR: No Soft Reset: No Soft Reset.
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PCI Express* Controller (x16) Registers 0 0 0 0 0 0 2 0 0 0 0 0 1 6 0 0 0 0 1 2 1 0 0 12.28 0 8 0 0 0 0 4 0 0 0 0 0 1 1 0 1 CID 0 2 4 RSVD 0 2 8 PNC 3 1 Bit Range Default & Access 31:16 0h RO Reserved (RSVD): Reserved. 15:8 80h RO PNC: Pointer to Next Capability: This contains a pointer to the next item in the capabilities list which is the PCI Power Management capability.
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PCI Express* Controller (x16) Registers 12.29 Message Signaled Interrupts Capability ID (MSI)—Offset 90h When a device supports MSI it can generate an interrupt request to the processor by writing a predefined data item (a message) to a predefined memory address. The reporting of the existence of this capability can be disabled by setting MSICH (CAPL[0] @ 7Fh). In that case walking this linked list will skip this capability and instead go directly from the PCI PM capability to the PCI Express capability.
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PCI Express* Controller (x16) Registers Bit Range 15:8 7 6:4 Default & Access Field Name (ID): Description 0h RO Reserved (RSVD): Reserved. 0h RO B64AC: 64-bit Address Capable: Hardwired to 0 to indicate that the function does not implement the upper 32 bits of the Message Address register and is incapable of generating a 64-bit memory address. This may need to change in future implementations when addressable system memory exceeds the 32b/4GB limit.
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PCI Express* Controller (x16) Registers 12.32 Message Data (MD)—Offset 98h Access Method Type: CFG (Size: 16 bits) Offset: [B:0, D:1, F:0] + 98h Default: 0h 15 0 0 8 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 MD 0 12 Bit Range Default & Access 0h RW 15:0 12.33 Field Name (ID): Description MD: Message Data: Base message data pattern assigned by system software and used to handle an MSI from the device.
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PCI Express* Controller (x16) Registers 12.34 PCI Express-G Capabilities (PEG)—Offset A2h Indicates PCI Express device capabilities. Access Method Type: CFG (Size: 16 bits) Offset: [B:0, D:1, F:0] + A2h Default: 142h 0 0 0 1 0 1 0 0 0 0 0 1 0 Bit Range Default & Access 15:14 0h RO Reserved (RSVD): Reserved. 13:9 0h RO IMN: Interrupt Message Number: Not Applicable or Implemented. Hardwired to 0.
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PCI Express* Controller (x16) Registers 0 0 0 0 0 0 0 0 0 0 0 0 0 12.36 1 2 1 0 0 0 8 0 0 0 0 4 0 0 RBER 0 0 0 0 0 0 1 MPS 0 1 6 PFS 0 2 0 RSVD 0 2 4 ETFS 2 8 RSVD 3 1 Bit Range Default & Access 31:16 0h RO Reserved (RSVD): Reserved. 15 1h RO RBER: Role Based Error Reporting: Role Based Error Reporting (RBER): Indicates that this device implements the functionality defined in the Error Reporting ECN as required by the PCI Express 1.1 spec.
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PCI Express* Controller (x16) Registers Bit Range Default & Access 15 0h RO Reserved (RSVD): Reserved. 14:12 0h RO MRRS: Reserved for Max Read Request Size: 11 0h RO NSE: Reserved for Enable No Snoop: 10:8 0h RO Reserved (RSVD): Reserved. 0h RW MPS: Max Payload Size: 001:256B max supported payload for Transaction Layer Packets (TLP). As a receiver, the Device should handle TLPs as large as the set value; as transmitter, the Device should not generate TLPs exceeding the set value.
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PCI Express* Controller (x16) Registers 0 0 Bit Range 15:6 Default & Access 1 0 12.38 0 0 0 0 0 0 0 Field Name (ID): Description Reserved (RSVD): Reserved. 0h RO TP: Transactions Pending: 0: All pending transactions (including completions for any outstanding non-posted requests on any used virtual channel) have been completed. 1: Indicates that the device has transaction(s) pending (including completions for any outstanding non-posted requests for all used Traffic Classes).
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PCI Express* Controller (x16) Registers 0 0 0 0 0 0 0 1 1 0 0 1 1 0 1 0 0 1 0 0 0 0 0 1 1 0 MLS 0 4 MLW 0 8 Active State Link PM Support 0 1 2 L0s Exit Latency 0 1 6 L1 Exit Latency 0 2 0 RSVD 0 2 4 RSVD 0 2 8 ASPM Optionality Compliance 3 1 Bit Range Default & Access 31:23 0h RO Reserved (RSVD): Reserved. 0h RO ASPM Optionality Compliance: This bit should be set to 1b in all Functions.
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PCI Express* Controller (x16) Registers 12.39 Link Control (LCTL)—Offset B0h Allows control of PCI Express link. Access Method Type: CFG (Size: 16 bits) Offset: [B:0, D:1, F:0] + B0h Default: 0h 0 0 0 0 0 0 0 0 0 ES CCC RL LD RCB RSVD 0 0 ASPM 0 ECPM 0 Bit Range Default & Access 15:12 0h RO Reserved (RSVD): Reserved.
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PCI Express* Controller (x16) Registers Bit Range Default & Access 0h RW CCC: Common Clock Configuration: 0: Indicates that this component and the component at the opposite end of this Link are operating with asynchronous reference clock. 1: Indicates that this component and the component at the opposite end of this Link are operating with a distributed common reference clock. The state of this bit affects the L0s Exit Latency reported in LCAP[14:12] and the N_FTS value advertised during link training.
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PCI Express* Controller (x16) Registers Bit Range Default & Access 0h RW1C LABWS: Link Autonomous Bandwidth Status: This bit is set to 1b by hardware to indicate that hardware has autonomously changed link speed or width, without the port transitioning through DL_Down status, for reasons other than to attempt to correct unreliable link operation.
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PCI Express* Controller (x16) Registers 12.41 Slot Capabilities (SLOTCAP)—Offset B4h PCI Express Slot related registers allow for the support of Hot Plug.
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PCI Express* Controller (x16) Registers Bit Range 12.42 Default & Access Field Name (ID): Description 2 0h RO MSP: Reserved for MRL Sensor Present: When set to 1b, this bit indicates that an MRL Sensor is implemented on the chassis for this slot. 1 0h RO PCP: Reserved for Power Controller Present: When set to 1b, this bit indicates that a software programmable Power Controller is implemented for this slot/adapter (depending on form factor).
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PCI Express* Controller (x16) Registers Bit Range Default & Access 0h RO PCC: Reserved for Power Controller Control: If a Power Controller is implemented, this field when written sets the power state of the slot per the defined encodings. Reads of this field should reflect the value from the latest write, even if the corresponding hotplug command is not complete, unless software issues a write without waiting for the previous command to complete in which case the read value is undefined.
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PCI Express* Controller (x16) Registers Bit Range Default & Access 2 0h RO MSCE: Reserved for MRL Sensor Changed Enable: When set to 1b, this bit enables software notification on a MRL sensor changed event. Default value of this field is 0b. If the MRL Sensor Present field in the Slot Capabilities register is set to 0b, this bit is permitted to be read-only with a value of 0b.
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PCI Express* Controller (x16) Registers Bit Range Default & Access Field Name (ID): Description 0h ROV PDS: Presence Detect State: --In band presence detect state: 0: Slot Empty 1: Card present in slot This bit indicates the presence of an adapter in the slot, reflected by the logical "OR" of the Physical Layer in-band presence detect mechanism and, if present, any out-ofband presence detect mechanism defined for the slot's corresponding form factor.
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PCI Express* Controller (x16) Registers 12.44 Root Control (RCTL)—Offset BCh Allows control of PCI Express Root Complex specific parameters. The system error control bits in this register determine if corresponding SERRs are generated when our device detects an error (reported in this device's Device Status register) or when an error message is received across the link. Reporting of SERR as controlled by these bits takes precedence over the SERR Enable in the PCI Command Register.
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PCI Express* Controller (x16) Registers 12.45 Root Status (RSTS)—Offset C0h Provides information about PCI Express Root Complex specific parameters. Access Method Type: CFG (Size: 32 bits) Offset: [B:0, D:1, F:0] + C0h Default: 0h 0 0 0 0 0 0 0 0 0 0 0 0 1 2 0 0 0 0 8 0 0 0 0 4 0 0 0 0 0 0 0 0 0 Bit Range Default & Access 31:18 0h RO Reserved (RSVD): Reserved. 0h RO PMEP: PME Pending: Indicates that another PME is pending when the PME Status bit is set.
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PCI Express* Controller (x16) Registers 0 0 0 0 0 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 CTOR 0 ARIFS 0 CTODS 0 ATOMIC32SUP 0 ATOMIC_OP_ROUTING_SUPPORT 0 0 Bit Range Default & Access 31:20 0h RO Reserved (RSVD): Reserved.
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PCI Express* Controller (x16) Registers Bit Range Default & Access 7 1h RO ATOMIC32SUP: 32-bit atomic operation completion support. Includes FetchAdd, Swap, and CAS AtomicOps. This bit should be set to 1b if the Function supports this optional capability. 6 0h RO ATOMIC_OP_ROUTING_SUPPORT: Atomic Operation Routing Supported. If set then atomic operations are supported.
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PCI Express* Controller (x16) Registers Bit Range Default & Access 15 0h RO Reserved (RSVD): Reserved. 14:13 0h RW OBFFEN: Reserved. 12:11 0h RO Reserved (RSVD): Reserved. 0h RW_V LTREN: Latency Tolerance Reporting Mechanism Enable: When Set to 1b, this bit enables the Latency Tolerance & Reporting (LTR) mechanism. This bit is required for all Functions that support the LTR Capability.
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PCI Express* Controller (x16) Registers Bit Range Default & Access 4 0 0 0 0 0 0 1 1 TLS 0 EC 0 HASD 0 selectabledeemphasis 0 Field Name (ID): Description ComplianceDeemphasis: Compliance De-emphasis: For 8 GT/s Data Rate: This field sets the Transmitter Preset level in Polling.Compliance state if the entry occurred due to the Enter Compliance bit being 1b. This bit sets the de-emphasis level in Polling.Compliance state if the entry occurred due to the Enter Compliance bit being 1b.
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PCI Express* Controller (x16) Registers Bit Range Default & Access 0h RWS_V txmargin: Transmit Margin: This field controls the value of the non-deemphasized voltage level at the Transmitter pins. This field is reset to 000b on entry to the LTSSM Polling.Configuration substrate (see Chapter 4 for details of how the transmitter voltage level is determined in various states).
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PCI Express* Controller (x16) Registers 0 0 Bit Range Default & Access 0 0 0 0 0 0 0 0 Field Name (ID): Description 0h RO Reserved (RSVD): Reserved. 5 0h RW1C LNKEQREQ: This bit is Set by hardware to request the Link equalization process to be performed on the Link. 4 0h ROV EQPH3SUCC: Equalization Phase 3 Successful When set to 1b, this bit indicates that Phase 3 of the Transmitter Equalization procedure has successfully completed.
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PCI Express* Controller (x16) Registers 0 0 0 0 0 0 0 0 0 1 6 0 0 0 0 1 2 0 0 0 0 8 0 0 0 0 4 0 0 Bit Range 0 Default & Access 0 0 0 0 Field Name (ID): Description 0h RO Reserved (RSVD): Reserved. 0h RO LPEVCC: Low Priority Extended VC Count: Indicates the number of (extended) Virtual Channels in addition to the default VC belonging to the low-priority VC (LPVC) group that has the lowest priority with respect to other VC resources in a strict-priority VC Arbitration.
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PCI Express* Controller (x16) Registers 12.52 Bit Range Default & Access 31:24 0h RO VCATO: VC Arbitration Table Offset: Indicates the location of the VC Arbitration Table. This field contains the zero-based offset of the table in DQWORDS (16 bytes) from the base address of the Virtual Channel Capability Structure. A value of 0 indicates that the table is not present (due to fixed VC priority). 23:8 0h RO Reserved (RSVD): Reserved.
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PCI Express* Controller (x16) Registers 0 0 0 0 RSVD 0 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 4 0 0 0 0 0 0 0 0 1 Bit Range Default & Access 31:24 0h RO PATO: Reserved for Port Arbitration Table Offset: 23 0h RO Reserved (RSVD): Reserved. 22:16 0h RO MTS: Reserved for Maximum Time Slots: 0h RO RSNPT: Reject Snoop Transactions: Reject Snoop Transactions (RSNPT): 0: Transactions with or without the No Snoop bit set within the TLP header are allowed on this VC.
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PCI Express* Controller (x16) Registers RSVD Bit Range Default & Access 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 1 1 1 1 0 1 1 1 1 Field Name (ID): Description 31 1h RO VC0E: VC0 Enable: For VC0 this is hardwired to 1 and read only as VC0 can never be disabled. 30:27 0h RO Reserved (RSVD): Reserved. 26:24 0h RO VC0ID: VC0 ID: Assigns a VC ID to the VC resource. For VC0 this is hardwired to 0 and read only. 23:20 0h RO Reserved (RSVD): Reserved.
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PCI Express* Controller (x16) Registers 0 0 8 0 0 0 4 0 0 0 0 0 0 0 Bit Range 15:2 Default & Access 12.56 0 0 Field Name (ID): Description 0h RO Reserved (RSVD): Reserved. 1h RO_V VC0NP: VC0 Negotiation Pending: 0: The VC negotiation is complete. 1: The VC resource is still in the process of negotiation (initialization or disabling). This bit indicates the status of the process of Flow Control initialization.
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PCI Express* Controller (x16) Registers Bit Range 12.57 Default & Access Field Name (ID): Description 11:5 0h RW1CS Reserved (RSVD): Reserved. 4 0h RW1CS DLPES: Data Link Protocol Error Status: The Data Link Layer Protocol Error that causes this bit to be set will also cause the Fatal Error Detected bit in Device Status[2] to be set if not already set. 3:0 0h RW1CS Reserved (RSVD): Reserved.
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PCI Express* Controller (x16) Registers 12.58 PEG Uncorrectable Error Severity—Offset 1CCh Controls whether an individual error is reported as a non-fatal or fatal error. An error is reported as fatal when the corresponding error bit in the severity register is set. If the bit is cleared, the corresponding error is considered nonfatal. This register is for test and debug purposes only. Access Method Type: CFG (Size: 32 bits) Offset: [B:0, D:1, F:0] + 1CCh Default: 0h 12.
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PCI Express* Controller (x16) Registers Bit Range 12.60 Default & Access Field Name (ID): Description 31:14 0h RW1CS Reserved (RSVD): Reserved. 13 0h RW1CS ANFES: Advisory Non-Fatal Error Status: Advisory Non-Fatal Error Status When set, indicates that an Advisory Non-Fatal Error occurred 12 0h RW1CS RTTS: Replay Timer Timeout Status 11:9 0h RW1CS Reserved (RSVD): Reserved.
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PCI Express* Controller (x16) Registers 12.61 PEG Advanced Error Capabilities and Control— Offset 1D8h The PCI Express Advanced Error Reporting (AER) capabilities defined through this register. First Error is logged here. Access Method Type: CFG (Size: 32 bits) Offset: [B:0, D:1, F:0] + 1D8h Default: 0h Bit Range 31:11 12.62 Default & Access 0h RO Field Name (ID): Description Reserved (RSVD): Reserved.
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PCI Express* Controller (x16) Registers 12.63 PEG Root Error Command—Offset 1ECh The Root Error Command register allows further control of Root Complex response to Correctable, Non-Fatal, and Fatal error Messages. Bit fields enable or disable generation of interrupts in addition to Do_SERR VDM sent to PCH. Access Method Type: CFG (Size: 32 bits) Offset: [B:0, D:1, F:0] + 1ECh Default: 0h Bit Range 12.64 Default & Access Field Name (ID): Description 31:3 0h RW Reserved (RSVD): Reserved.
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PCI Express* Controller (x16) Registers Bit Range 12.65 Default & Access Field Name (ID): Description 2 0h RW1CS EFNFR: ERR_FATAL/NONFATAL Received: Set when either a fatal or a non-fatal error message is received and this bit is not already set. 1 0h RW1CS MECR: Multiple ERR_COR Received: 0 0h RW1CS ECR: ERR_COR Received: Set when a correctable error message is received and this bit is not already set.
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PCI Express* Controller (x8) Registers 13 PCI Express* Controller (x8) Registers Table 13-1.
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PCI Express* Controller (x8) Registers Table 13-1.
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PCI Express* Controller (x8) Registers 13.1 Vendor Identification (VID)—Offset 0h This register combined with the Device Identification register uniquely identify any PCI device. Access Method Type: CFG (Size: 16 bits) Offset: [B:0, D:1, F:1] + 0h Default: 8086h 15 0 0 0 8 0 0 0 4 0 1 0 0 0 0 0 1 1 0 VID 1 12 Bit Range Default & Access 8086h RO 15:0 13.2 Field Name (ID): Description VID: Vendor Identification: PCI standard identification for Intel.
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PCI Express* Controller (x8) Registers 13.3 PCI Command (PCICMD)—Offset 4h Access Method Type: CFG (Size: 16 bits) Offset: [B:0, D:1, F:1] + 4h Default: 0h 420 0 0 0 0 0 0 0 0 0 0 0 PERRE VGAPS MWIE SCE BME MAE IOAE 0 0 RSVD 0 4 SERRE 0 8 FB2B 0 RSVD 0 12 INTAAD 15 Bit Range Default & Access 15:11 0h RO Reserved (RSVD): Reserved. 10 0h RW INTAAD: INTA Assertion Disable: 0:This device is permitted to generate INTA interrupt messages.
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PCI Express* Controller (x8) Registers Bit Range 13.4 Default & Access Field Name (ID): Description 2 0h RW BME: Bus Master Enable: Bus Master Enable (BME): Controls the ability of the PEG port to forward Memory Read/Write Requests in the upstream direction. 0: This device is prevented from making memory requests to its primary bus.
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PCI Express* Controller (x8) Registers Bit Range Field Name (ID): Description 15 0h RW1C DPE: Detected Parity Error: This bit is Set by a Function whenever it receives a Poisoned TLP, regardless of the state the Parity Error Response bit in the Command register. On a Function with a Type 1 Configuration header, the bit is Set when the Poisoned TLP is received by its Primary Side. Default value of this bit is 0b. This bit will be set only for completions of requests encountering ECC error in DRAM.
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PCI Express* Controller (x8) Registers Bit Range 1h RO 4 3 2:0 13.5 Default & Access Field Name (ID): Description CAPL: Capabilities List: Indicates that a capabilities list is present. Hardwired to 1. 0h ROV INTAS: INTx Status: Indicates that an interrupt message is pending internally to the device. Only PME and Hot Plug sources feed into this status bit (not PCI INTA-INTD assert and de-assert messages). The INTA Assertion Disable bit, PCICMD1[10], has no effect on this bit.
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PCI Express* Controller (x8) Registers 0 0 1 6 0 0 1 1 0 1 2 0 0 0 13.7 8 0 0 1 0 0 4 0 0 0 0 0 SUBCC BCC 0 2 0 0 0 0 0 PI 2 3 Bit Range Default & Access 23:16 6h RO BCC: Base Class Code: Indicates the base class code for this device. This code has the value 06h, indicating a Bridge device. 15:8 4h RO SUBCC: Sub-Class Code: Indicates the sub-class code for this device. The code is 04h indicating a PCI to PCI Bridge.
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PCI Express* Controller (x8) Registers 7 4 0 0 0 0 0 0 0 1 HDR 1 Bit Range 7:0 13.9 Default & Access Field Name (ID): Description HDR: Header Type Register: Device #1 returns 81 to indicate that this is a multi function device with bridge header layout. Device #6 returns 01 to indicate that this is a single function device with bridge header layout. 81h RO Primary Bus Number (PBUSN)—Offset 18h This register identifies that this "virtual" Host-PCI Express bridge is connected to PCI bus #0.
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PCI Express* Controller (x8) Registers 7 4 0 0 0 0 0 0 0 0 BUSN 0 Bit Range 7:0 13.11 Default & Access 0h RW Field Name (ID): Description BUSN: Secondary Bus Number: This field is programmed by configuration software with the bus number assigned to PCI Express-G. Subordinate Bus Number (SUBUSN)—Offset 1Ah This register identifies the subordinate bus (if any) that resides at the level below PCI Express-G.
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PCI Express* Controller (x8) Registers Default: F0h 7 4 1 1 0 1 0 0 Bit Range 13.13 0 0 RSVD IOBASE 1 Default & Access Field Name (ID): Description 7:4 Fh RW IOBASE: I/O Address Base: Corresponds to A[15:12] of the I/O addresses passed by the root port to PCI Express-G. 3:0 0h RO Reserved (RSVD): Reserved.
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PCI Express* Controller (x8) Registers 13.14 Secondary Status (SSTS)—Offset 1Eh SSTS is a 16-bit status register that reports the occurrence of error conditions associated with secondary side (i.e. PCI Express-G side) of the "virtual" PCI-PCI bridge embedded within the processor.
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PCI Express* Controller (x8) Registers 13.15 Memory Base Address (MBASE)—Offset 20h This register controls the Processor to PCI Express-G non-prefetchable memory access routing based on the following formula: MEMORY_BASE=< address =<MEMORY_LIMIT The upper 12 bits of the register are read/write and correspond to the upper 12 address bits A[31:20] of the 32 bit address. The bottom 4 bits of this register are readonly and return zeros when read.
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PCI Express* Controller (x8) Registers in a true plug-and-play manner to the prefetchable address range for improved CPUPCI Express memory access performance. Note also that configuration software is responsible for programming all address range registers (prefetchable, non-prefetchable) with the values that provide exclusive address ranges i.e. prevent overlap with each other and/or with the ranges covered with the main memory.
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PCI Express* Controller (x8) Registers 15 12 1 1 1 8 1 1 1 1 4 1 1 1 1 0 0 0 Bit Range Default & Access 15:4 3:0 13.18 0 1 AS64 PMBASE 1 Field Name (ID): Description FFFh RW PMBASE: Prefetchable Memory Base Address: Corresponds to A[31:20] of the lower limit of the memory range that will be passed to PCI Express-G.
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PCI Express* Controller (x8) Registers Bit Range 13.19 Default & Access Field Name (ID): Description 15:4 0h RW PMLIMIT: Prefetchable Memory Address Limit: Corresponds to A[31:20] of the upper limit of the address range passed to PCI Express-G.
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PCI Express* Controller (x8) Registers 13.20 Prefetchable Memory Limit Address Upper (PMLIMITU)—Offset 2Ch The functionality associated with this register is present in the PEG design implementation.
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PCI Express* Controller (x8) Registers 13.21 Capabilities Pointer (CAPPTR)—Offset 34h The capabilities pointer provides the address offset to the location of the first entry in this device's linked list of capabilities. Access Method Type: CFG (Size: 8 bits) Offset: [B:0, D:1, F:1] + 34h Default: 88h 7 4 0 0 0 1 0 0 0 CAPPTR1 1 0 Bit Range 7:0 13.
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PCI Express* Controller (x8) Registers 13.23 Interrupt Pin (INTRPIN)—Offset 3Dh This register specifies which interrupt pin this device uses. Access Method Type: CFG (Size: 8 bits) Offset: [B:0, D:1, F:1] + 3Dh Default: 1h 4 0 0 0 0 0 INTPINH 0 0 Bit Range 7:3 2:0 13.
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PCI Express* Controller (x8) Registers 0 0 0 0 0 0 0 0 0 SRESET MAMODE VGA16D VGAEN ISAEN SERREN PEREN 0 0 FB2BEN 4 0 PDT 8 0 Bit Range Default & Access 15:12 0h RO Reserved (RSVD): Reserved. 11 0h RO DTSERRE: Discard Timer SERR# Enable: Not Applicable or Implemented. Hardwired to 0. 10 0h RO DTSTS: Discard Timer Status: Not Applicable or Implemented. Hardwired to 0. 9 0h RO SDT: Secondary Discard Timer: Not Applicable or Implemented. Hardwired to 0.
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PCI Express* Controller (x8) Registers 13.
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PCI Express* Controller (x8) Registers 13.26 Power Management Control/Status (PM)—Offset 84h Access Method Type: CFG (Size: 32 bits) Offset: [B:0, D:1, F:1] + 84h Default: 8h 0 0 0 0 0 0 0 0 438 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 PS 0 0 NSR 0 4 RSVD 0 8 RSVD 0 1 2 PMEE 0 1 6 DSEL 0 2 0 DSCALE 0 2 4 RSVD 0 2 8 PMESTS 3 1 Bit Range Default & Access 31:16 0h RO Reserved (RSVD): Reserved.
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PCI Express* Controller (x8) Registers Bit Range 3 1h RO 2 0h RO Field Name (ID): Description NSR: No Soft Reset: No Soft Reset. When set to 1 this bit indicates that the device is transitioning from D3hot to D0 because the power state commands do not perform a internal reset. Config context is preserved. Upon transition no additional operating sys intervention is required to preserve configuration context beyond writing the power state bits.
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PCI Express* Controller (x8) Registers 13.28 Bit Range Default & Access 31:16 0h RO Reserved (RSVD): Reserved. 15:8 80h RO PNC: Pointer to Next Capability: This contains a pointer to the next item in the capabilities list which is the PCI Power Management capability. 7:0 Dh RO CID: Capability ID: Value of 0Dh identifies this linked list item (capability structure) as being for SSID/SSVID registers in a PCI-to-PCI Bridge.
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PCI Express* Controller (x8) Registers 13.29 Message Signaled Interrupts Capability ID (MSI)—Offset 90h When a device supports MSI it can generate an interrupt request to the processor by writing a predefined data item (a message) to a predefined memory address. The reporting of the existence of this capability can be disabled by setting MSICH (CAPL[0] @ 7Fh). In that case walking this linked list will skip this capability and instead go directly from the PCI PM capability to the PCI Express capability.
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PCI Express* Controller (x8) Registers Bit Range 13.31 Default & Access Field Name (ID): Description 15:8 0h RO Reserved (RSVD): Reserved. 7 0h RO B64AC: 64-bit Address Capable: Hardwired to 0 to indicate that the function does not implement the upper 32 bits of the Message Address register and is incapable of generating a 64-bit memory address. This may need to change in future implementations when addressable system memory exceeds the 32b/4GB limit.
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PCI Express* Controller (x8) Registers 13.32 Message Data (MD)—Offset 98h Access Method Type: CFG (Size: 16 bits) Offset: [B:0, D:1, F:1] + 98h Default: 0h 15 0 0 8 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 MD 0 12 Bit Range Default & Access 13.33 MD: Message Data: Base message data pattern assigned by system software and used to handle an MSI from the device. When the device should generate an interrupt request, it writes a 32-bit value to the memory address specified in the MA register.
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PCI Express* Controller (x8) Registers 13.34 PCI Express-G Capabilities (PEG)—Offset A2h Indicates PCI Express device capabilities. Access Method Type: CFG (Size: 16 bits) Offset: [B:0, D:1, F:1] + A2h Default: 142h 0 0 0 1 0 1 0 0 0 0 0 1 0 Bit Range Default & Access 15:14 0h RO Reserved (RSVD): Reserved. 13:9 0h RO IMN: Interrupt Message Number: Not Applicable or Implemented. Hardwired to 0.
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PCI Express* Controller (x8) Registers 0 0 0 0 0 0 0 0 0 0 0 0 0 13.36 1 2 1 0 0 0 8 0 0 0 0 4 0 0 RBER 0 0 0 0 0 0 1 MPS 0 1 6 PFS 0 2 0 RSVD 0 2 4 ETFS 2 8 RSVD 3 1 Bit Range Default & Access 31:16 0h RO Reserved (RSVD): Reserved. 15 1h RO RBER: Role Based Error Reporting: Role Based Error Reporting (RBER): Indicates that this device implements the functionality defined in the Error Reporting ECN as required by the PCI Express 1.1 spec.
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PCI Express* Controller (x8) Registers Bit Range 13.37 Default & Access Field Name (ID): Description 15 0h RO Reserved (RSVD): Reserved. 14:12 0h RO MRRS: Reserved for Max Read Request Size: 11 0h RO NSE: Reserved for Enable No Snoop: 10:8 0h RO Reserved (RSVD): Reserved. 7:5 0h RW MPS: Max Payload Size: 001:256B max supported payload for Transaction Layer Packets (TLP).
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PCI Express* Controller (x8) Registers 0 0 Bit Range 0 0 0 0 0 0 0 0 Field Name (ID): Description 0h RO Reserved (RSVD): Reserved. 5 0h RO TP: Transactions Pending: 0: All pending transactions (including completions for any outstanding non-posted requests on any used virtual channel) have been completed. 1: Indicates that the device has transaction(s) pending (including completions for any outstanding non-posted requests for all used Traffic Classes). Not Applicable or Implemented.
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PCI Express* Controller (x8) Registers 448 0 0 0 0 0 0 0 1 1 0 0 1 1 0 1 0 0 1 0 0 0 0 0 1 1 0 MLS 0 4 MLW 0 8 Active State Link PM Support 0 1 2 L0s Exit Latency 0 1 6 L1 Exit Latency 0 2 0 RSVD 0 2 4 RSVD 0 2 8 ASPM Optionality Compliance 3 1 Bit Range Default & Access 31:23 0h RO Reserved (RSVD): Reserved. 22 0h RO ASPM Optionality Compliance: This bit should be set to 1b in all Functions.
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PCI Express* Controller (x8) Registers 13.39 Link Control (LCTL)—Offset B0h Allows control of PCI Express link. Access Method Type: CFG (Size: 16 bits) Offset: [B:0, D:1, F:1] + B0h Default: 0h 0 0 0 0 0 0 0 0 0 CCC RL LD RCB RSVD 0 0 ASPM 0 ES 0 ECPM 0 4 HAWD 0 8 LBMIE 0 RSVD 0 12 LABIE 15 Bit Range Default & Access 15:12 0h RO Reserved (RSVD): Reserved.
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PCI Express* Controller (x8) Registers Bit Range Default & Access 0h RW CCC: Common Clock Configuration: 0: Indicates that this component and the component at the opposite end of this Link are operating with asynchronous reference clock. 1: Indicates that this component and the component at the opposite end of this Link are operating with a distributed common reference clock. The state of this bit affects the L0s Exit Latency reported in LCAP[14:12] and the N_FTS value advertised during link training.
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PCI Express* Controller (x8) Registers Bit Range Default & Access Field Name (ID): Description 0h RW1C LABWS: Link Autonomous Bandwidth Status: This bit is set to 1b by hardware to indicate that hardware has autonomously changed link speed or width, without the port transitioning through DL_Down status, for reasons other than to attempt to correct unreliable link operation.
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PCI Express* Controller (x8) Registers 13.41 Slot Capabilities (SLOTCAP)—Offset B4h PCI Express Slot related registers allow for the support of Hot Plug.
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PCI Express* Controller (x8) Registers Bit Range 13.42 Default & Access Field Name (ID): Description 2 0h RO MSP: Reserved for MRL Sensor Present: When set to 1b, this bit indicates that an MRL Sensor is implemented on the chassis for this slot. 1 0h RO PCP: Reserved for Power Controller Present: When set to 1b, this bit indicates that a software programmable Power Controller is implemented for this slot/adapter (depending on form factor).
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PCI Express* Controller (x8) Registers Bit Range Field Name (ID): Description 0h RO PIC: Reserved Power Indicator Control: Reserved Power Indicator Control (PIC): If a Power Indicator is implemented, writes to this field set the Power Indicator to the written state.
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PCI Express* Controller (x8) Registers 13.43 Slot Status (SLOTSTS)—Offset BAh PCI Express Slot related registers. Access Method Type: CFG (Size: 16 bits) Offset: [B:0, D:1, F:1] + BAh Default: 0h Bit Range Default & Access 0 0 0 0 0 0 0 0 0 MSC PFD ABP 0 PDC 0 CC 0 0 MSS 0 4 PDS 0 8 EIS 0 RSVD 0 12 DLLSC 15 Field Name (ID): Description 15:9 0h RO Reserved (RSVD): Reserved.
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PCI Express* Controller (x8) Registers Bit Range 13.44 Default & Access Field Name (ID): Description 4 0h RO CC: Reserved for Command Completed: If Command Completed notification is supported (as indicated by No Command Completed Support field of Slot Capabilities Register), this bit is set when a hot-plug command has completed and the Hot-Plug Controller is ready to accept a subsequent command.
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PCI Express* Controller (x8) Registers Bit Range Field Name (ID): Description 31:5 0h RO Reserved (RSVD): Reserved. 4 0h RO CSVE: Reserved for CRS Software Visibility Enable: This bit, when set, enables the Root Port to return Configuration Request Retry Status (CRS) Completion Status to software. Root Ports that do not implement this capability should hardwire this bit to 0b. 3 0h RW PMEIE: PME Interrupt Enable: 0: No interrupts are generated as a result of receiving PME messages.
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PCI Express* Controller (x8) Registers Bit Range Default & Access 31:18 0h RO Reserved (RSVD): Reserved. 17 0h RO PMEP: PME Pending: Indicates that another PME is pending when the PME Status bit is set. When the PME Status bit is cleared by software; the PME is delivered by hardware by setting the PME Status bit again and updating the Requestor ID appropriately. The PME pending bit is cleared by hardware if no more PMEs are pending.
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PCI Express* Controller (x8) Registers Bit Range Default & Access 31:20 0h RO Reserved (RSVD): Reserved.
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PCI Express* Controller (x8) Registers Bit Range Default & Access 5 4 3:0 13.47 Field Name (ID): Description 0h RO ARIFS: ARI Forwarding Supported: Applicable only to Switch Downstream Ports and Root Ports; should be 0b for other Function types. This bit should be set to 1b if a Switch Downstream Port or Root Port supports this optional capability. 0h RO CTODS: Completion Timeout Disabled Supported: A value of 1b indicates support for the Completion Timeout Disable mechanism.
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PCI Express* Controller (x8) Registers Bit Range Default & Access 10 0h RW_V 9:7 0h RO LTREN: Latency Tolerance Reporting Mechanism Enable: When Set to 1b, this bit enables the Latency Tolerance & Reporting (LTR) mechanism. This bit is required for all Functions that support the LTR Capability. For a MultiFunction device associated with an upstream port of a device that implements LTBWR, the bit in Function 0 is of type RW, and only Function 0 controls the components Link behavior.
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PCI Express* Controller (x8) Registers Bit Range 15:12 11 10 9:7 6 462 Default & Access Field Name (ID): Description 0h RWS ComplianceDeemphasis: Compliance De-emphasis: For 8 GT/s Data Rate: This field sets the Transmitter Preset level in Polling.Compliance state if the entry occurred due to the Enter Compliance bit being 1b. This bit sets the de-emphasis level in Polling.Compliance state if the entry occurred due to the Enter Compliance bit being 1b. Defined encodings are: 0001b -3.
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PCI Express* Controller (x8) Registers Bit Range Default & Access 5 0h RWS HASD: Hardware Autonomous Speed Disable: When set to 1b this bit disables hardware from changing the link speed for reasons other than attempting to correct unreliable link operation by reducing link speed.
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PCI Express* Controller (x8) Registers Bit Range Field Name (ID): Description 2 0h ROV EQPH1SUCC: Equalization Phase 1 Successful When set to 1b, this bit indicates that Phase 1 of the Transmitter Equalization procedure has successfully completed. 1 0h ROV EQCOMPLETE: Equalization Complete When set to 1b, this bit indicates that the Transmitter Equalization procedure has completed.
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PCI Express* Controller (x8) Registers 13.51 Port VC Capability Register 2 (PVCCAP2)—Offset 108h Describes the configuration of PCI Express Virtual Channels associated with this port. Access Method Type: CFG (Size: 32 bits) Offset: [B:0, D:1, F:1] + 108h Default: 0h 2 8 0 0 0 0 0 0 0 2 0 0 0 0 0 1 6 0 0 0 0 13.
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PCI Express* Controller (x8) Registers Bit Range 13.53 Default & Access Field Name (ID): Description 15:4 0h RO Reserved (RSVD): Reserved. 3:1 0h RW VCAS: VC Arbitration Select: This field will be programmed by software to the only possible value as indicated in the VC Arbitration Capability field. Since there is no other VC supported than the default, this field is reserved.
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PCI Express* Controller (x8) Registers Bit Range Default & Access 15 0h RO 14:8 0h RO RSNPT: Reject Snoop Transactions: Reject Snoop Transactions (RSNPT): 0: Transactions with or without the No Snoop bit set within the TLP header are allowed on this VC. 1: When Set, any transaction for which the No Snoop attribute is applicable but is not Set within the TLP Header will be rejected as an Unsupported Request Reserved (RSVD): Reserved.
PAGE 442
PCI Express* Controller (x8) Registers Bit Range 13.55 Default & Access Field Name (ID): Description 31 1h RO VC0E: VC0 Enable: For VC0 this is hardwired to 1 and read only as VC0 can never be disabled. 30:27 0h RO Reserved (RSVD): Reserved. 26:24 0h RO VC0ID: VC0 ID: Assigns a VC ID to the VC resource. For VC0 this is hardwired to 0 and read only. 23:20 0h RO Reserved (RSVD): Reserved.
PAGE 443
PCI Express* Controller (x8) Registers Bit Range Field Name (ID): Description 0h RO Reserved (RSVD): Reserved. 1 1h RO_V VC0NP: VC0 Negotiation Pending: 0: The VC negotiation is complete. 1: The VC resource is still in the process of negotiation (initialization or disabling). This bit indicates the status of the process of Flow Control initialization. It is set by default on Reset, as well as whenever the corresponding Virtual Channel is Disabled or the Link is in the DL_Down state.
PAGE 444
PCI Express* Controller (x8) Registers 13.57 PEG Uncorrectable Error Mask—Offset 1C8h Controls reporting of individual errors by the device (or logic associated with this port) to the PCI Express Root Complex. As these errors are not originating on the other side of a PCI Express link, no PCI Express error message is sent, but the unmasked error is reported directly to the root control logic. A masked error (respective bit set to 1 in the mask register) has no action taken.
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PCI Express* Controller (x8) Registers Bit Range 13.59 Default & Access Field Name (ID): Description 31:21 0h RWS Reserved (RSVD): Reserved.
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PCI Express* Controller (x8) Registers 13.60 PEG Correctable Error Mask—Offset 1D4h Controls reporting of individual correctable errors by the device (or logic associated with this port) to the PCI Express Root Complex. As these errors are not originating on the other side of a PCI Express link, no PCI Express error message is sent, but the unmasked error is reported directly to the root control logic. A masked error (respective bit set to 1 in the mask register) has no action taken.
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PCI Express* Controller (x8) Registers Bit Range 13.62 Default & Access Field Name (ID): Description 8 0h RO ECRCCE: ECRC Check Enable 7 0h RO ECRCCC: ECRC Check Capable 6 0h RO ECRCGE: ECRC Generation Enable 5 0h R0 ECRCGC: ECRC Generation Capable 4:0 0h ROS FEP: First Error Pointer PEG Header Log—Offset 1DCh, 1E0h, 1E4h, 1E8h The PCI Express Advanced Error Reporting (AER) capability for header logging will use this register for a header log.
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PCI Express* Controller (x8) Registers 13.64 PEG Root Error Status—Offset 1F0h The Root Error Status register reports status of error messages received by the root complex, and of errors detected by the Root Port itself (which are treated conceptually as if the Root Port had sent an error message to itself). This register is updated regardless of the settings of the Root Control register and the Root Error Command register (which is not even implemented).
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PCI Express* Controller (x4) Registers 14 PCI Express* Controller (x4) Registers Table 14-1.
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PCI Express* Controller (x4) Registers Table 14-1.
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PCI Express* Controller (x4) Registers 14.1 Vendor Identification (VID)—Offset 0h This register combined with the Device Identification register uniquely identify any PCI device. Access Method Type: CFG (Size: 16 bits) Offset: [B:0, D:1, F:2] + 0h Default: 8086h 15 0 0 0 8 0 0 0 4 0 1 0 0 0 0 0 1 1 0 VID 1 12 Bit Range Default & Access 8086h RO 15:0 14.2 Field Name (ID): Description VID: Vendor Identification: PCI standard identification for Intel.
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PCI Express* Controller (x4) Registers 14.3 PCI Command (PCICMD)—Offset 4h Access Method Type: CFG (Size: 16 bits) Offset: [B:0, D:1, F:2] + 4h Default: 0h 478 0 0 0 0 0 0 0 0 0 0 0 PERRE VGAPS MWIE SCE BME MAE IOAE 0 0 RSVD 0 4 SERRE 0 8 FB2B 0 RSVD 0 12 INTAAD 15 Bit Range Default & Access 15:11 0h RO Reserved (RSVD): Reserved. 10 0h RW INTAAD: INTA Assertion Disable: 0: This device is permitted to generate INTA interrupt messages.
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PCI Express* Controller (x4) Registers Bit Range 14.4 Default & Access Field Name (ID): Description 2 0h RW BME: Bus Master Enable: Bus Master Enable (BME): Controls the ability of the PEG port to forward Memory Read/Write Requests in the upstream direction. 0: This device is prevented from making memory requests to its primary bus.
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PCI Express* Controller (x4) Registers Bit Range Field Name (ID): Description 15 0h RW1C DPE: Detected Parity Error: This bit is Set by a Function whenever it receives a Poisoned TLP, regardless of the state the Parity Error Response bit in the Command register. On a Function with a Type 1 Configuration header, the bit is Set when the Poisoned TLP is received by its Primary Side. Default value of this bit is 0b. This bit will be set only for completions of requests encountering ECC error in DRAM.
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PCI Express* Controller (x4) Registers Bit Range 1h RO 4 3 2:0 14.5 Default & Access Field Name (ID): Description CAPL: Capabilities List: Indicates that a capabilities list is present. Hardwired to 1. 0h ROV INTAS: INTx Status: Indicates that an interrupt message is pending internally to the device. Only PME and Hot Plug sources feed into this status bit (not PCI INTA-INTD assert and de-assert messages). The INTA Assertion Disable bit, PCICMD1[10], has no effect on this bit.
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PCI Express* Controller (x4) Registers 0 0 1 6 0 0 1 1 0 1 2 0 0 0 14.7 8 0 0 1 0 0 4 0 0 0 0 0 SUBCC BCC 0 2 0 0 0 0 0 PI 2 3 Bit Range Default & Access 23:16 6h RO BCC: Base Class Code: Indicates the base class code for this device. This code has the value 06h, indicating a Bridge device. 15:8 4h RO SUBCC: Sub-Class Code: Indicates the sub-class code for this device. The code is 04h indicating a PCI to PCI Bridge.
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PCI Express* Controller (x4) Registers 7 4 0 0 0 0 0 0 0 1 HDR 1 Bit Range 7:0 14.9 Default & Access Field Name (ID): Description HDR: Header Type Register: Device #1 returns 81 to indicate that this is a multi function device with bridge header layout. Device #6 returns 01 to indicate that this is a single function device with bridge header layout. 81h RO Primary Bus Number (PBUSN)—Offset 18h This register identifies that this "virtual" Host-PCI Express bridge is connected to PCI bus #0.
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PCI Express* Controller (x4) Registers 7 4 0 0 0 0 0 0 0 0 BUSN 0 Bit Range 7:0 14.11 Default & Access 0h RW Field Name (ID): Description BUSN: Secondary Bus Number: This field is programmed by configuration software with the bus number assigned to PCI Express-G. Subordinate Bus Number (SUBUSN)—Offset 1Ah This register identifies the subordinate bus (if any) that resides at the level below PCI Express-G.
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PCI Express* Controller (x4) Registers Type: CFG (Size: 8 bits) Offset: [B:0, D:1, F:2] + 1Ch Default: F0h 7 4 1 1 1 0 0 Bit Range 14.13 0 0 RSVD IOBASE 1 0 Default & Access Field Name (ID): Description 7:4 Fh RW IOBASE: I/O Address Base: Corresponds to A[15:12] of the I/O addresses passed by the root port to PCI Express-G. 3:0 0h RO Reserved (RSVD): Reserved.
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PCI Express* Controller (x4) Registers 14.14 Secondary Status (SSTS)—Offset 1Eh SSTS is a 16-bit status register that reports the occurrence of error conditions associated with secondary side (i.e. PCI Express-G side) of the "virtual" PCI-PCI bridge embedded within the processor.
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PCI Express* Controller (x4) Registers 14.15 Memory Base Address (MBASE)—Offset 20h This register controls the Processor to PCI Express-G non-prefetchable memory access routing based on the following formula: MEMORY_BASE=< address =<MEMORY_LIMIT The upper 12 bits of the register are read/write and correspond to the upper 12 address bits A[31:20] of the 32 bit address. The bottom 4 bits of this register are readonly and return zeros when read.
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PCI Express* Controller (x4) Registers in a true plug-and-play manner to the prefetchable address range for improved CPUPCI Express memory access performance. Note also that configuration software is responsible for programming all address range registers (prefetchable, non-prefetchable) with the values that provide exclusive address ranges i.e. prevent overlap with each other and/or with the ranges covered with the main memory.
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PCI Express* Controller (x4) Registers 15 12 1 1 1 8 1 1 1 1 4 1 1 1 1 0 0 0 Bit Range Default & Access 15:4 3:0 14.18 0 1 AS64 PMBASE 1 Field Name (ID): Description FFFh RW PMBASE: Prefetchable Memory Base Address: Corresponds to A[31:20] of the lower limit of the memory range that will be passed to PCI Express-G.
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PCI Express* Controller (x4) Registers Bit Range 14.19 Default & Access Field Name (ID): Description 15:4 0h RW PMLIMIT: Prefetchable Memory Address Limit: Corresponds to A[31:20] of the upper limit of the address range passed to PCI Express-G.
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PCI Express* Controller (x4) Registers 14.20 Prefetchable Memory Limit Address Upper (PMLIMITU)—Offset 2Ch The functionality associated with this register is present in the PEG design implementation.
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PCI Express* Controller (x4) Registers 14.21 Capabilities Pointer (CAPPTR)—Offset 34h The capabilities pointer provides the address offset to the location of the first entry in this device's linked list of capabilities. Access Method Type: CFG (Size: 8 bits) Offset: [B:0, D:1, F:2] + 34h Default: 88h 7 4 0 0 0 1 0 0 0 CAPPTR1 1 0 Bit Range 7:0 14.
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PCI Express* Controller (x4) Registers 14.23 Interrupt Pin (INTRPIN)—Offset 3Dh This register specifies which interrupt pin this device uses. Access Method Type: CFG (Size: 8 bits) Offset: [B:0, D:1, F:2] + 3Dh Default: 1h 4 0 0 0 0 0 INTPINH 0 0 Bit Range 7:3 2:0 14.
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PCI Express* Controller (x4) Registers 0 0 0 0 0 0 0 0 0 SRESET MAMODE VGA16D VGAEN ISAEN SERREN PEREN 0 0 FB2BEN 4 0 PDT 8 0 Bit Range Default & Access 15:12 0h RO Reserved (RSVD): Reserved. 11 0h RO DTSERRE: Discard Timer SERR# Enable: Not Applicable or Implemented. Hardwired to 0. 10 0h RO DTSTS: Discard Timer Status: Not Applicable or Implemented. Hardwired to 0. 9 0h RO SDT: Secondary Discard Timer: Not Applicable or Implemented. Hardwired to 0.
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PCI Express* Controller (x4) Registers 14.
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PCI Express* Controller (x4) Registers 14.26 Power Management Control/Status (PM)—Offset 84h Access Method Type: CFG (Size: 32 bits) Offset: [B:0, D:1, F:2] + 84h Default: 8h 0 0 0 0 0 0 0 0 496 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 PS 0 0 NSR 0 4 RSVD 0 8 RSVD 0 1 2 PMEE 0 1 6 DSEL 0 2 0 DSCALE 0 2 4 RSVD 0 2 8 PMESTS 3 1 Bit Range Default & Access 31:16 0h RO Reserved (RSVD): Reserved.
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PCI Express* Controller (x4) Registers Bit Range 3 1h RO 2 0h RO Field Name (ID): Description NSR: No Soft Reset: No Soft Reset. When set to 1 this bit indicates that the device is transitioning from D3hot to D0 because the power state commands do not perform a internal reset. Config context is preserved. Upon transition no additional operating sys intervention is required to preserve configuration context beyond writing the power state bits.
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PCI Express* Controller (x4) Registers 14.28 Bit Range Default & Access 31:16 0h RO Reserved (RSVD): Reserved. 15:8 80h RO PNC: Pointer to Next Capability: This contains a pointer to the next item in the capabilities list which is the PCI Power Management capability. 7:0 Dh RO CID: Capability ID: Value of 0Dh identifies this linked list item (capability structure) as being for SSID/SSVID registers in a PCI-to-PCI Bridge.
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PCI Express* Controller (x4) Registers 14.29 Message Signaled Interrupts Capability ID (MSI)—Offset 90h When a device supports MSI it can generate an interrupt request to the processor by writing a predefined data item (a message) to a predefined memory address. The reporting of the existence of this capability can be disabled by setting MSICH (CAPL[0] @ 7Fh). In that case walking this linked list will skip this capability and instead go directly from the PCI PM capability to the PCI Express capability.
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PCI Express* Controller (x4) Registers Bit Range 14.31 Default & Access Field Name (ID): Description 15:8 0h RO Reserved (RSVD): Reserved. 7 0h RO B64AC: 64-bit Address Capable: Hardwired to 0 to indicate that the function does not implement the upper 32 bits of the Message Address register and is incapable of generating a 64-bit memory address. This may need to change in future implementations when addressable system memory exceeds the 32b/4GB limit.
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PCI Express* Controller (x4) Registers 14.32 Message Data (MD)—Offset 98h Access Method Type: CFG (Size: 16 bits) Offset: [B:0, D:1, F:2] + 98h Default: 0h 15 0 0 8 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 MD 0 12 Bit Range Default & Access 14.33 MD: Message Data: Base message data pattern assigned by system software and used to handle an MSI from the device. When the device should generate an interrupt request, it writes a 32-bit value to the memory address specified in the MA register.
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PCI Express* Controller (x4) Registers 14.34 PCI Express-G Capabilities (PEG)—Offset A2h Indicates PCI Express device capabilities. Access Method Type: CFG (Size: 16 bits) Offset: [B:0, D:1, F:2] + A2h Default: 142h 0 0 0 1 0 1 0 0 0 0 0 1 0 Bit Range Default & Access 15:14 0h RO Reserved (RSVD): Reserved. 13:9 0h RO IMN: Interrupt Message Number: Not Applicable or Implemented. Hardwired to 0.
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PCI Express* Controller (x4) Registers 0 0 0 0 0 0 0 0 0 0 0 0 0 14.36 1 2 1 0 0 0 8 0 0 0 0 4 0 0 RBER 0 0 0 0 0 0 1 MPS 0 1 6 PFS 0 2 0 RSVD 0 2 4 ETFS 2 8 RSVD 3 1 Bit Range Default & Access 31:16 0h RO Reserved (RSVD): Reserved. 15 1h RO RBER: Role Based Error Reporting: Role Based Error Reporting (RBER): Indicates that this device implements the functionality defined in the Error Reporting ECN as required by the PCI Express 1.1 spec.
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PCI Express* Controller (x4) Registers Bit Range 14.37 Default & Access Field Name (ID): Description 15 0h RO Reserved (RSVD): Reserved. 14:12 0h RO MRRS: Reserved for Max Read Request Size: 11 0h RO NSE: Reserved for Enable No Snoop: 10:8 0h RO Reserved (RSVD): Reserved. 7:5 0h RW MPS: Max Payload Size: 001:256B max supported payload for Transaction Layer Packets (TLP).
PAGE 479
PCI Express* Controller (x4) Registers Bit Range Field Name (ID): Description 0h RO Reserved (RSVD): Reserved. 5 0h RO TP: Transactions Pending: 0: All pending transactions (including completions for any outstanding non-posted requests on any used virtual channel) have been completed. 1: Indicates that the device has transaction(s) pending (including completions for any outstanding non-posted requests for all used Traffic Classes). Not Applicable or Implemented. Hardwired to 0. 4 0h RO 15:6 14.
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PCI Express* Controller (x4) Registers 506 0 0 0 0 0 0 0 1 1 0 0 1 1 0 1 0 0 1 0 0 0 0 0 1 1 0 MLS 0 4 MLW 0 8 Active State Link PM Support 0 1 2 L0s Exit Latency 0 1 6 L1 Exit Latency 0 2 0 RSVD 0 2 4 RSVD 0 2 8 ASPM Optionality Compliance 3 1 Bit Range Default & Access 31:23 0h RO Reserved (RSVD): Reserved. 22 0h RO ASPM Optionality Compliance: This bit should be set to 1b in all Functions.
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PCI Express* Controller (x4) Registers 14.39 Link Control (LCTL)—Offset B0h Allows control of PCI Express link. Access Method Type: CFG (Size: 16 bits) Offset: [B:0, D:1, F:2] + B0h Default: 0h 0 0 0 0 0 0 0 0 0 CCC RL LD RCB RSVD 0 0 ASPM 0 ES 0 ECPM 0 4 HAWD 0 8 LBMIE 0 RSVD 0 12 LABIE 15 Bit Range Default & Access 15:12 0h RO Reserved (RSVD): Reserved.
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PCI Express* Controller (x4) Registers Bit Range Default & Access 0h RW CCC: Common Clock Configuration: 0: Indicates that this component and the component at the opposite end of this Link are operating with asynchronous reference clock. 1: Indicates that this component and the component at the opposite end of this Link are operating with a distributed common reference clock. The state of this bit affects the L0s Exit Latency reported in LCAP[14:12] and the N_FTS value advertised during link training.
PAGE 483
PCI Express* Controller (x4) Registers Bit Range Default & Access Field Name (ID): Description 0h RW1C LABWS: Link Autonomous Bandwidth Status: This bit is set to 1b by hardware to indicate that hardware has autonomously changed link speed or width, without the port transitioning through DL_Down status, for reasons other than to attempt to correct unreliable link operation.
PAGE 484
PCI Express* Controller (x4) Registers 14.41 Slot Capabilities (SLOTCAP)—Offset B4h PCI Express Slot related registers allow for the support of Hot Plug.
PAGE 485
PCI Express* Controller (x4) Registers Bit Range 14.42 Default & Access Field Name (ID): Description 2 0h RO MSP: Reserved for MRL Sensor Present: When set to 1b, this bit indicates that an MRL Sensor is implemented on the chassis for this slot. 1 0h RO PCP: Reserved for Power Controller Present: When set to 1b, this bit indicates that a software programmable Power Controller is implemented for this slot/adapter (depending on form factor).
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PCI Express* Controller (x4) Registers Bit Range Field Name (ID): Description 0h RO PIC: Reserved Power Indicator Control: Reserved Power Indicator Control (PIC): If a Power Indicator is implemented, writes to this field set the Power Indicator to the written state.
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PCI Express* Controller (x4) Registers 14.43 Slot Status (SLOTSTS)—Offset BAh PCI Express Slot related registers. Access Method Type: CFG (Size: 16 bits) Offset: [B:0, D:1, F:2] + BAh Default: 0h Bit Range Default & Access 0 0 0 0 0 0 0 0 0 MSC PFD ABP 0 PDC 0 CC 0 0 MSS 0 4 PDS 0 8 EIS 0 RSVD 0 12 DLLSC 15 Field Name (ID): Description 15:9 0h RO Reserved (RSVD): Reserved.
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PCI Express* Controller (x4) Registers Bit Range 14.44 Default & Access Field Name (ID): Description 4 0h RO CC: Reserved for Command Completed: If Command Completed notification is supported (as indicated by No Command Completed Support field of Slot Capabilities Register), this bit is set when a hot-plug command has completed and the Hot-Plug Controller is ready to accept a subsequent command.
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PCI Express* Controller (x4) Registers Bit Range Field Name (ID): Description 31:5 0h RO Reserved (RSVD): Reserved. 4 0h RO CSVE: Reserved for CRS Software Visibility Enable: This bit, when set, enables the Root Port to return Configuration Request Retry Status (CRS) Completion Status to software. Root Ports that do not implement this capability should hardwire this bit to 0b. 3 0h RW PMEIE: PME Interrupt Enable: 0: No interrupts are generated as a result of receiving PME messages.
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PCI Express* Controller (x4) Registers Bit Range Default & Access 31:18 0h RO Reserved (RSVD): Reserved. 17 0h RO PMEP: PME Pending: Indicates that another PME is pending when the PME Status bit is set. When the PME Status bit is cleared by software; the PME is delivered by hardware by setting the PME Status bit again and updating the Requestor ID appropriately. The PME pending bit is cleared by hardware if no more PMEs are pending.
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PCI Express* Controller (x4) Registers Bit Range Default & Access 31:20 0h RO Reserved (RSVD): Reserved.
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PCI Express* Controller (x4) Registers Bit Range Default & Access 5 4 3:0 14.47 Field Name (ID): Description 0h RO ARIFS: ARI Forwarding Supported: Applicable only to Switch Downstream Ports and Root Ports; should be 0b for other Function types. This bit should be set to 1b if a Switch Downstream Port or Root Port supports this optional capability. 0h RO CTODS: Completion Timeout Disabled Supported: A value of 1b indicates support for the Completion Timeout Disable mechanism.
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PCI Express* Controller (x4) Registers Bit Range Default & Access 10 0h RW_V 9:7 0h RO LTREN: Latency Tolerance Reporting Mechanism Enable: When Set to 1b, this bit enables the Latency Tolerance & Reporting (LTR) mechanism. This bit is required for all Functions that support the LTR Capability. For a MultiFunction device associated with an upstream port of a device that implements LTBWR, the bit in Function 0 is of type RW, and only Function 0 controls the components Link behavior.
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PCI Express* Controller (x4) Registers Bit Range 15:12 11 10 9:7 6 520 Default & Access Field Name (ID): Description 0h RWS ComplianceDeemphasis: Compliance De-emphasis: For 8 GT/s Data Rate: This field sets the Transmitter Preset level in Polling.Compliance state if the entry occurred due to the Enter Compliance bit being 1b. This bit sets the de-emphasis level in Polling.Compliance state if the entry occurred due to the Enter Compliance bit being 1b. Defined encodings are: 0001b -3.
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PCI Express* Controller (x4) Registers Bit Range Default & Access 5 0h RWS HASD: Hardware Autonomous Speed Disable: When set to 1b this bit disables hardware from changing the link speed for reasons other than attempting to correct unreliable link operation by reducing link speed.
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PCI Express* Controller (x4) Registers Bit Range Field Name (ID): Description 2 0h ROV EQPH1SUCC: Equalization Phase 1 Successful When set to 1b, this bit indicates that Phase 1 of the Transmitter Equalization procedure has successfully completed. 1 0h ROV EQCOMPLETE: Equalization Complete When set to 1b, this bit indicates that the Transmitter Equalization procedure has completed.
PAGE 497
PCI Express* Controller (x4) Registers 14.51 Port VC Capability Register 2 (PVCCAP2)—Offset 108h Describes the configuration of PCI Express Virtual Channels associated with this port. Access Method Type: CFG (Size: 32 bits) Offset: [B:0, D:1, F:2] + 108h Default: 0h 2 8 0 0 0 0 0 0 0 2 0 0 0 0 0 1 6 0 0 0 0 14.
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PCI Express* Controller (x4) Registers Bit Range 14.53 Default & Access Field Name (ID): Description 15:4 0h RO Reserved (RSVD): Reserved. 3:1 0h RW VCAS: VC Arbitration Select: This field will be programmed by software to the only possible value as indicated in the VC Arbitration Capability field. Since there is no other VC supported than the default, this field is reserved.
PAGE 499
PCI Express* Controller (x4) Registers Bit Range Default & Access 15 0h RO 14:8 0h RO RSNPT: Reject Snoop Transactions: Reject Snoop Transactions (RSNPT): 0: Transactions with or without the No Snoop bit set within the TLP header are allowed on this VC. 1: When Set, any transaction for which the No Snoop attribute is applicable but is not Set within the TLP Header will be rejected as an Unsupported Request Reserved (RSVD): Reserved.
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PCI Express* Controller (x4) Registers Bit Range 14.55 Default & Access Field Name (ID): Description 31 1h RO VC0E: VC0 Enable: For VC0 this is hardwired to 1 and read only as VC0 can never be disabled. 30:27 0h RO Reserved (RSVD): Reserved. 26:24 0h RO VC0ID: VC0 ID: Assigns a VC ID to the VC resource. For VC0 this is hardwired to 0 and read only. 23:20 0h RO Reserved (RSVD): Reserved.
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PCI Express* Controller (x4) Registers Bit Range Field Name (ID): Description 0h RO Reserved (RSVD): Reserved. 1 1h RO_V VC0NP: VC0 Negotiation Pending: 0: The VC negotiation is complete. 1: The VC resource is still in the process of negotiation (initialization or disabling). This bit indicates the status of the process of Flow Control initialization. It is set by default on Reset, as well as whenever the corresponding Virtual Channel is Disabled or the Link is in the DL_Down state.
PAGE 502
PCI Express* Controller (x4) Registers 14.57 PEG Uncorrectable Error Mask—Offset 1C8h Controls reporting of individual errors by the device (or logic associated with this port) to the PCI Express Root Complex. As these errors are not originating on the other side of a PCI Express link, no PCI Express error message is sent, but the unmasked error is reported directly to the root control logic. A masked error (respective bit set to 1 in the mask register) has no action taken.
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PCI Express* Controller (x4) Registers Bit Range 14.59 Default & Access Field Name (ID): Description 31:21 0h RWS Reserved (RSVD): Reserved.
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PCI Express* Controller (x4) Registers 14.60 PEG Correctable Error Mask—Offset 1D4h Controls reporting of individual correctable errors by the device (or logic associated with this port) to the PCI Express Root Complex. As these errors are not originating on the other side of a PCI Express link, no PCI Express error message is sent, but the unmasked error is reported directly to the root control logic. A masked error (respective bit set to 1 in the mask register) has no action taken.
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PCI Express* Controller (x4) Registers Bit Range 14.62 Default & Access Field Name (ID): Description 8 0h RO ECRCCE: ECRC Check Enable 7 0h RO ECRCCC: ECRC Check Capable 6 0h RO ECRCGE: ECRC Generation Enable 5 0h R0 ECRCGC: ECRC Generation Capable 4:0 0h ROS FEP: First Error Pointer PEG Header Log—Offset 1DCh, 1E0h, 1E4h, 1E8h The PCI Express Advanced Error Reporting (AER) capability for header logging will use this register for a header log.
PAGE 506
PCI Express* Controller (x4) Registers 14.64 PEG Root Error Status—Offset 1F0h The Root Error Status register reports status of error messages received by the root complex, and of errors detected by the Root Port itself (which are treated conceptually as if the Root Port had sent an error message to itself). This register is updated regardless of the settings of the Root Control register and the Root Error Command register (which is not even implemented).
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GTTMMADR Registers 15 GTTMMADR Registers Table 15-1.
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GTTMMADR Registers Access Method Type: MEM (Size: 32 bits) Offset: [B:0, D:2, F:0] + 108000h Default: 100000h 0 0 0 0 0 0 2 0 0 0 0 1 1 6 0 0 0 0 1 2 0 0 0 Bit Range 31:20 19:1 0 15.2 0 8 0 0 0 0 4 0 0 0 0 0 0 Default & Access 0 0 0 LOCK 0 2 4 TOLUD 0 2 8 RSVD 3 1 Field Name (ID): Description 1h RO_V TOLUD: This register contains bits 31 to 20 of an address one byte above the maximum DRAM memory below 4G that is usable by the operating system.
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GTTMMADR Registers Access Method Type: MEM (Size: 64 bits) Offset: [B:0, D:2, F:0] + 108080h Default: 0h 6 3 6 0 5 6 5 2 4 8 4 4 4 0 3 6 3 2 2 8 2 4 2 0 1 6 1 2 8 4 0 LOCK Bit Range Default & Access 63:39 0h RO Reserved (RSVD): Reserved. 0h RO_V TOUUD: This register contains bits 38 to 20 of an address one byte above the maximum DRAM memory above 4G that is usable by the operating system.
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GTTMMADR Registers 0 0 0 2 4 0 0 0 0 2 0 0 0 0 0 1 6 0 0 0 0 1 2 0 0 0 0 8 0 0 0 0 0 0 0 0 0 0 0 Bit Range Default & Access 31:20 0h RO_V BDSM: This register contains bits 31 to 20 of the base address of stolen DRAM memory. BIOS determines the base of graphics stolen memory by subtracting the graphics stolen memory size (PCI Device 0 offset 50 bits 15:8) from TOLUD (PCI Device 0 offset BC bits 31:20). 0h RO Reserved (RSVD): Reserved.
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GTTMMADR Registers Bit Range Default & Access 31:20 1h RO_V BGSM: This register contains the base address of stolen DRAM memory for the GTT. BIOS determines the base of GTT stolen memory by subtracting the GTT graphics stolen memory size (PCI Device 0 offset 50 bits 7:6) from the Graphics Base of Data Stolen Memory (PCI Device 0 offset B0 bits 31:20). 0h RO Reserved (RSVD): Reserved. 0h RO_V LOCK: This bit will lock all writeable settings in this register, including itself. 19:1 0 15.
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GTTMMADR Registers Bit Range 31 30:1 0 15.6 Default & Access 0h RO_V 0h RO 0h RO_V Field Name (ID): Description EPM: This field controls DMA accesses to the protected low-memory and protected high-memory regions. 0: Protected memory regions are disabled. 1: Protected memory regions are enabled. DMA requests accessing protected memory regions are handled as follows: • When DMA remapping is not enabled, all DMA requests accessing protected memory regions are blocked.
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GTTMMADR Registers Default: 0h 3 1 0 0 0 2 4 0 0 0 0 2 0 0 0 0 0 1 6 0 0 0 0 0 0 0 0 8 0 0 0 0 4 0 0 0 0 0 0 0 0 Bit Range Default & Access 31:20 0h RO_V PLMB: This register specifies the base of protected low-memory region in system memory. 0h RO Reserved (RSVD): Reserved. 19:0 15.
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GTTMMADR Registers 3 1 0 0 2 4 0 0 0 0 2 0 0 0 0 0 1 6 0 0 0 0 1 2 0 0 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Range Default & Access 31:20 0h RO_V PLML: This register specifies the last host physical address of the DMA-protected lowmemory region in system memory. 0h RO Reserved (RSVD): Reserved. 19:0 15.
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GTTMMADR Registers Bit Range Default & Access 63:39 0h RO Reserved (RSVD): Reserved. 38:20 0h RO_V PHMB: This register specifies the base of protected (high) memory region in system memory. Hardware ignores, and does not implement, bits 63:HAW, where HAW is the host address width. 0h RO Reserved (RSVD): Reserved. 19:0 15.9 Field Name (ID): Description Protected High-Memory Limit Register (MPHMLIMIT)—Offset 108280h Register to set up the limit address of DMA-protected high-memory region.
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GTTMMADR Registers 6 3 6 0 5 6 5 2 4 8 4 4 4 0 3 6 3 2 2 8 2 4 2 0 1 6 1 2 8 4 0 RSVD Bit Range Default & Access 63:39 0h RO Reserved (RSVD): Reserved. 38:20 0h RO_V PHML: This register specifies the last host physical address of the DMA-protected high-memory region in system memory. Hardware ignores and does not implement bits 63:HAW, where HAW is the host address width. 0h RO Reserved (RSVD): Reserved. 19:0 15.
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GTTMMADR Registers Bit Range Default & Access 31:20 0h RO_V 19:7 0h RO_V 6 0h RO_V 5 0h RO_V 4 0h RO_V OVTATTACK: Override of Unsolicited Connection State Attack and Terminate. 0: Disable Override. Attack Terminate allowed. 1: Enable Override. Attack Terminate disallowed. This register bit is locked when PAVPE is set. 3 0h RO_V HVYMODSEL: This bit is applicable only for PAVP2 operation mode.
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GTTMMADR Registers 15.11 Global Command Register (MGCMD)—Offset 108300h Register to control remapping hardware. If multiple control fields in this register need to be modified, software should serialize the modifications through multiple writes to this register.
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GTTMMADR Registers Bit Range 29 28 27 26 25 Datasheet, Volume 2 of 2 Default & Access Field Name (ID): Description 0h RO SFL: This field is valid only for implementations supporting advanced fault logging. Software sets this field to request hardware to set/update the fault-log pointer used by hardware. The fault-log pointer is specified through Advanced Fault Log register. Hardware reports the status of the 'Set Fault Log' operation through the FLS field in the Global Status register.
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GTTMMADR Registers Bit Range 24 23 22:0 Default & Access Field Name (ID): Description 0h WO SIRTP: This field is valid only for implementations supporting interrupt-remapping. Software sets this field to set/update the interrupt remapping table pointer used by hardware. The interrupt remapping table pointer is specified through the Interrupt Remapping Table Address (IRTA_REG) register.