User Guide

8 Datasheet, Volume 1 of 2
2-24 S-Processor Line Display Resolution Configuration (DP@30 Hz)....................................43
2-25 HDCP Display supported Implications Table ................................................................44
2-26 Display Link Data Rate Support ................................................................................44
2-27 Display Resolution and Link Rate Support ..................................................................44
2-28 Display Bit Per Pixel (BPP) Support...........................................................................45
2-29 Supported Resolutions1 for HBR (2.7 Gbps) by Link Width ..........................................45
2-30 Supported Resolutions1 for HBR2 (5.4 Gbps) by Link Width.........................................45
4-1 System States........................................................................................................63
4-2 Processor IA Core / Package State Support ................................................................64
4-3 Integrated Memory Controller (IMC) States ................................................................64
4-4 PCI Express* Link States .........................................................................................64
4-5 Direct Media Interface (DMI) States ..........................................................................64
4-6 G, S, and C Interface State Combinations ..................................................................65
4-7 Deepest Package C-State Available ...........................................................................72
4-8 Targeted Memory State Conditions............................................................................75
4-9 Package C-States with PCIe* Link States dependencies ...............................................76
5-1 Configurable TDP Modes ..........................................................................................83
5-2 TDP Specifications (S-Processor Line)........................................................................92
5-3 Package Turbo Specifications (S-Processor Line) .........................................................92
5-4 Low Power and TTV Specifications (S-Processor Line) ..................................................93
5-5 T
CONTROL
Offset Configuration (S-Processor Line - Client) .............................................94
5-6 Thermal Test Vehicle Thermal Profile for PCG 2015D Processor .....................................95
5-7 Thermal Test Vehicle Thermal Profile for PCG 2015C Processor .....................................96
5-8 Thermal Test Vehicle Thermal Profile for PCG 2015B Processor .....................................97
5-9 Thermal Test Vehicle Thermal Profile for PCG 2015A Processor .....................................98
5-10 Digital Thermal Sensor (DTS) 1.1 Thermal Solution Performance Above T
CONTROL
..........101
5-11 Thermal Margin Slope ........................................................................................... 102
6-1 Signal Tables Terminology ..................................................................................... 103
6-2 DDR3L/-RS Memory Interface ................................................................................ 103
6-3 DDR4 Memory Interface ........................................................................................ 105
6-4 System Memory Reference and Compensation Signals ............................................... 106
6-5 PCI Express* Interface .......................................................................................... 106
6-6 DMI Interface Signals............................................................................................ 106
6-7 Reset and Miscellaneous Signals ............................................................................. 107
6-8 embedded DisplayPort* Signals ..............................................................................107
6-9 Display Interface Signals .......................................................................................108
6-10 Processor Clocking Signals .....................................................................................108
6-11 Testability Signals.................................................................................................109
6-12 Error and Thermal Protection Signals....................................................................... 109
6-13 Power Sequencing Signals .....................................................................................110
6-14 Processor Power Rails Signals................................................................................. 111
6-15 GND, RSVD, and NCTF Signals ............................................................................... 112
6-16 Processor Internal Pull-Up / Pull-Down Terminations..................................................112
7-1 Processor Power Rails............................................................................................113
7-2 Processor IA core (Vcc) Active and Idle Mode DC Voltage and Current Specifications...... 114
7-3 Processor Graphics (Vcc
GT
) Supply DC Voltage and Current Specifications ...................116
7-4 Memory Controller (VDDQ) Supply DC Voltage and Current Specifications ....................117
7-5 System Agent (VccSA) Supply DC Voltage and Current Specifications .......................... 118
7-6 Processor I/O (Vcc
IO
) Supply DC Voltage and Current Specifications ............................ 118
7-7 Vcc Sustain (VccST) Supply DC Voltage and Current Specifications .............................. 119
7-8 Processor PLL (VccPLL) Supply DC Voltage and Current Specifications.......................... 119
7-9 Processor PLL_OC (VccPLL_OC) Supply DC Voltage and Current Specifications ..............119
7-10 DDR3L/-RS Signal Group DC Specifications ..............................................................120
7-11 DDR4 Signal Group DC Specifications ...................................................................... 121
7-12 PCI Express* Graphics (PEG) Group DC Specifications ...............................................122