User Guide

Technologies
58 Datasheet, Volume 1 of 2
active if the operating system is requesting the P0 state. If turbo frequencies are
limited the cause is logged in IA_PERF_LIMIT_REASONS register. For more information
on P-states and C-states, see Power Management.
3.3.3 Intel
®
Advanced Vector Extensions 2 (Intel
®
AVX2)
Intel
®
Advanced Vector Extensions 2.0 (Intel
®
AVX2) is the latest expansion of the
Intel instruction set. Intel AVX2 extends the Intel Advanced Vector Extensions (Intel
AVX) with 256-bit integer instructions, floating-point fused multiply add (FMA)
instructions, and gather operations. The 256-bit integer vectors benefit math, codec,
image, and digital signal processing software. FMA improves performance in face
detection, professional imaging, and high performance computing. Gather operations
increase vectorization opportunities for many applications. In addition to the vector
extensions, this generation of Intel processors adds new bit manipulation instructions
useful in compression, encryption, and general purpose software.
For more information on Intel AVX, see http://www.intel.com/software/avx
Intel Advanced Vector Extensions (Intel AVX) are designed to achieve higher
throughput to certain integer and floating point operation. Due to varying processor
power characteristics, utilizing AVX instructions may cause a) parts to operate below
the base frequency b) some parts with Intel
Turbo Boost Technology 2.0 to not achieve
any or maximum turbo frequencies. Performance varies depending on hardware,
software and system configuration and you should consult your system manufacturer
for more information. Intel
Advanced Vector Extensions refers to Intel AVX, Intel AVX2
or Intel AVX-512.
For more information on Intel AVX, see http://www-ssl.intel.com/content/www/us/en/
architecture-and-technology/turbo-boost/turbo-boost-technology.html
Note: Intel AVX2 Technology may not be available on all SKUs.
3.3.4 Intel
®
64 Architecture x2APIC
The x2APIC architecture extends the xAPIC architecture that provides key mechanisms
for interrupt delivery. This extension is primarily intended to increase processor
addressability.
Specifically, x2APIC:
• Retains all key elements of compatibility to the xAPIC architecture:
— Delivery modes
— Interrupt and processor priorities
— Interrupt sources
— Interrupt destination types
• Provides extensions to scale processor addressability for both the logical and
physical destination modes
• Adds new features to enhance performance of interrupt delivery
• Reduces complexity of logical destination mode interrupt delivery on link based
architectures