User Guide

Datasheet, Volume 1 of 2 45
Interfaces
2.5.10 Display Bit Per Pixel (BPP) Support
2.5.11 Display Resolution per Link Width
2.6 Platform Environmental Control Interface (PECI)
PECI is an Intel proprietary interface that provides a communication channel between
Intel processors and external components like Super IO (SIO) and Embedded
Controllers (EC) to provide processor temperature, Turbo, Configurable TDP, and
3200x1800 5.4 (HBR2) QHD+
2880x1800 2.7 (HBR) QHD
2880x1620 2.7 (HBR) QHD
2560x1600 2.7 (HBR) QHD
2560x1440 2.7 (HBR) QHD
1920x1080 1.62 (RBR) FHD
Table 2-28. Display Bit Per Pixel (BPP) Support
Technology Bit Per Pixel (bpp)
eDP* 24,30,36
DisplayPort* 24,30,36
HDMI* 24,36
Table 2-29. Supported Resolutions
1
for HBR (2.7 Gbps) by Link Width
Link Width
Max Link Bandwidth
[Gbps]
Max Pixel Clock
(theoretical) [MHz]
S-Processor Lines
4 lanes 10.8 360 2880x1800 @ 60 Hz, 24bpp
2 lanes 5.4 180 2048x1280 @ 60 Hz, 24bpp
1 lane 2.7 90 1280x960 @ 60 Hz, 24bpp
Notes:
1. The examples assumed 60 Hz refresh rate and 24 bpp.
Table 2-30. Supported Resolutions
1
for HBR2 (5.4 Gbps) by Link Width
Link Width
Max Link Bandwidth
[Gbps]
Max Pixel Clock
(theoretical) [MHz]
S-Processor Lines
4 lanes 21.6 720
2
See “Maximum Display
Resolutions” table
2 lanes 10.8 360 2880x1800 @ 60 Hz, 24bpp
1 lane 5.4 180 2048x1280 @ 60 Hz, 24bpp
Notes:
1. The examples assumed 60 Hz refresh rate and 24 bpp.
2. The actual Max pixel clock for HBR2 is limited by the CD clock to 675 MHz for S-Processor Line.
Table 2-27. Display Resolution and Link Rate Support (Sheet 2 of 2)
Resolution
Link Rate
Support
High Definition