User Guide

Interfaces
26 Datasheet, Volume 1 of 2
2.1.8 Data Swapping
By default, the processor supports on-board data swapping in two manners (for all
segments and DRAM technologies):
• byte (DQ+DQS) swapping between bytes in the same channel.
• bit swapping within specific byte.
2.1.9 DRAM Clock Generation
Every supported rank has a differential clock pair. There are a total of four clock pairs
driven directly by the processor to DRAM.
2.1.10 DRAM Reference Voltage Generation
The memory controller has the capability of generating the DDR3L/-RS, and DDR4
Reference Voltage (VREF) internally for both read and write operations. The generated
VREF can be changed in small steps, and an optimum VREF value is determined for
both during a cold boot through advanced training procedures in order to provide the
best voltage to achieve the best signal margins.
2.1.11 Data Swizzling
All Processor Lines does not have die-to-package DDR swizzling.
2.2 PCI Express* Graphics Interface (PEG)
This section describes the PCI Express* interface capabilities of the processor. See the
PCI Express Base* Specification 3.0 for details on PCI Express*.
2.2.1 PCI Express* Support
The processor’s PCI Express* interface is a 16-lane (x16) port that can also be
configured as multiple ports at narrower widths (see Table 2-11, Table 2-12).
The processor supports the configurations shown in the following table.