User Guide

Datasheet, Volume 1 of 2 19

Interfaces

2 Interfaces

2.1 System Memory Interface

• Two channels of DDR3L/-RS, and DDR4 memory with a maximum of two DIMMs

per channel. DDR technologies, number of DIMMs per channel, number of ranks

per channel are SKU dependent.

• UDIMM, SO-DIMM, and Memory Down support (based on SKU)

• Single-channel and dual-channel memory organization modes

• Data burst length of eight for all memory organization modes

• DDR3L/-RS I/O Voltage of 1.35V - based on Processor Line

• DDR4 I/O Voltage of 1.2V

• 64-bit wide channels

• Non-ECC UDIMM and SODIMM DDR4/DDR3L/-RS support (based on SKU)

• Theoretical maximum memory bandwidth of:

— 20.8 GB/s in dual-channel mode assuming 1333 MT/s

— 25.0 GB/s in dual-channel mode assuming 1600 MT/s

— 33.3 GB/s in dual-channel mode assuming 2133 MT/s

— 37.5 GB/s in dual-channel mode assuming 2400 MT/s

Note: Memory down of all technologies (DDR3L/DDR4) should be implemented

homogeneously, which means that all DRAM devices should be from the same vendor

and have the same part number. Implementing a mix of DRAM devices may cause

serious signal integrity and functional issues.

Note: If the S-Processor Lines memory interface is configured to one DIMM per Channel, the

processor can use either of the DIMMs, DIMM0 or DIMM1, signals CTRL[1:0] or

CTRL[3:2].

2.1.1 System Memory Technology Supported

The Integrated Memory Controller (IMC) supports DDR3L/-RS, and DDR4 protocols

with two independent, 64-bit wide channels.

Table 2-1. Processor DRAM Support Matrix

Processor Line DPC

DDR3L/-RS [MT/s] DDR4 [MT/s] LPDDR3 [MT/s]

S-Processor Line 2 1333/1600 2133

/2400 N/A

Notes:

1. DPC = DIMM Per Channel

2. N/A

3. S-Processor SO-DIMM 2DPC is limited to 2133 MT/s due to Daisy Chain topology.