User Guide

Electrical Specifications
124 Datasheet, Volume 1 of 2
Vcc
ST
nominal levels will vary between processor families. All PECI devices will operate
at the Vcc
ST
level determined by the processor installed in the system.
Input Device Hysteresis
The input buffers in both client and host models should use a Schmitt-triggered input
design for improved noise immunity. Use the following figure as a guide for input buffer
design.
§ §
Table 7-17. PECI DC Electrical Limits
Symbol Definition and Conditions Min Max Units Notes
1
R
up
Internal pull up resistance 15 45  3
V
IN
Input Voltage Range -0.15 Vcc
ST
+ 0.15 V -
V
Hysteresis
Hysteresis 0.15 * Vcc
ST
—V -
V
IL
Input Voltage Low- Edge
Threshold Voltage
— 0.3 * Vcc
ST
V -
V
IH
Input Voltage High-Edge
Threshold Voltage
0.7 * Vcc
ST
— V -
C
bus
Bus Capacitance per Node N/A 10 pF -
C
pad
Pad Capacitance 0.7 1.8 pF -
Ileak000 leakage current @ 0V — 0.6 mA -
Ileak025 leakage current @ 0.25* Vcc
ST
— 0.4 mA -
Ileak050 leakage current @ 0.50* Vcc
ST
— 0.2 mA -
Ileak075 leakage current @ 0.75* Vcc
ST
— 0.13 mA -
Ileak100 leakage current @ Vcc
ST
— 0.10 mA -
Notes:
1. Vcc
ST
supplies the PECI interface. PECI behavior does not affect Vcc
ST
min/max specifications.
2. The leakage specification applies to powered devices on the PECI bus.
3. The PECI buffer internal pull up resistance measured at 0.75* Vcc
ST
.
Figure 7-1. Input Device Hysteresis
Minimum V
P
Maximum V
P
Minimum V
N
Maximum V
N
PECI High Range
PECI Low Range
Valid Input
Signal Range
Minimum
Hysteresis
V
TTD
PECI Ground