User Guide

Electrical Specifications
120 Datasheet, Volume 1 of 2
7.2.2 Processor Interfaces DC Specifications
7.2.2.1 DDR3L/-RS DC Specifications
Table 7-10. DDR3L/-RS Signal Group DC Specifications
Symbol Parameter
S-Processor Line
Units Notes
1
Min Typ Max
V
IL
Input Low Voltage
— —
0.43*
V
DDQ
V
2, 4, 8,
9
V
IH
Input High Voltage 0.57*
V
DDQ
— — V
3, 4, 8,
9
R
ON_UP/DN(DQ)
DDR3L/-RS Data Buffer pull-up/down Resistance Trainable  10
R
ODT(DQ)
DDR3L/-RS On-die termination equivalent resistance
for data signals
Trainable  10
V
ODT(DC)
DDR3L/-RS On-die termination DC working point
(driver set to receive mode)
0.45*
V
DDQ
0.5*
V
DDQ
0.55*
V
DDQ
V 10
R
ON_UP/DN(CK)
DDR3L/-RS Clock Buffer pull-up/down Resistance 0.8*Typ 26 1.2*Typ  5, 10
R
ON_UP/DN(CMD)
DDR3L/-RS Command Buffer pull-up/down Resistance 0.8*Typ 20 1.2*Typ  10
R
ON_UP/DN(CTL)
DDR3L/-RS Control Buffer pull-up/down Resistance 0.8*Typ 20 1.2*Typ  5, 10
R
ON_UP/DN
(DDR_VTT_CNTL)
System Memory Power Gate Control Buffer Pull-Up/
down Resistance
40 — 140 
I
LI
Input Leakage Current (DQ, CK)
0 V
0.2*V
DDQ
0.8*V
DDQ
— — 1 mA
DDR0_Vref_DQ
DDR1_Vref_DQ
DDR_Vref_CA
VREF output voltage Trainable V
DDQ
/2 Trainable V 9,11
DDR_RCOMP[0] ODT resistance compensation
RCOMP values are memory
topology dependent.
 6
DDR_RCOMP[1] Data resistance compensation  6
DDR_RCOMP[2] Command resistance compensation  6
Notes:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. V
IL
is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value.
3. V
IH
is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value.
4. V
IH
and V
IL
may experience excursions above V
DDQ
. However, input signal drivers should comply with the signal quality
specifications.
5. This is the pull up/down driver resistance after compensation. Note that BIOS power training may change these values
significantly based on margin/power trade-off.
6.
7. DDR_VREF is defined as V
DDQ
/2 for DDR3L/-RS
8. R
ON
tolerance is preliminary and might be subject to change.
9. Processor may be damaged if V
IH
exceeds the maximum voltage for extended periods.
10. Final value determined by BIOS power training, values might vary between bytes and/or units.
11. The value will be set during the MRC boot training within the specified range.
12. DDR0_Vref_DQ - Not in use in DDR4, DDR1_Vref_DQ = DDR4_CA_ch1, DDR_Vref_CA = DD4_CA_ch0.