User Guide

Datasheet, Volume 1 of 2 119
Electrical Specifications
7.2.1.6 Vcc
ST
DC Specifications
7.2.1.7 Vcc
PLL
DC Specifications
Table 7-7. Vcc Sustain (Vcc
ST
) Supply DC Voltage and Current Specifications
Symbol Parameter Segment Min Typ Max Units Notes
1,2
Vcc
ST
Processor Vcc Sustain
supply voltage
All — 1.0 — V 3
TOB
ST
Vcc
ST
Tolerance All AC+DC:± 50 mV 3
Icc
MAX_ST
Max Current for Vcc
ST
S-Processor Lines — — 60 mA
Notes:
1. Unless otherwise noted, all specifications in this table are based on estimates and simulations or empirical data. These
specifications will be updated with characterized data from silicon measurements at a later date.
2. Long term reliability cannot be assured in conditions above or below Max/Min functional limits.
3. The voltage specification requirements are measured on package pins as near as possible to the processor with an
oscilloscope set to 100-MHz bandwidth, 1.5 pF maximum probe capacitance, and 1 M minimum impedance. The maximum
length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled into the
oscilloscope probe.
Table 7-8. Processor PLL (Vcc
PLL
) Supply DC Voltage and Current Specifications
Symbol Parameter Segment Min Typ Max Unit Notes
1,2
Vcc
PLL
PLL supply voltage (DC + AC
specification)
All — 1.0 — V 3
TOB
CCPLL
Vcc
PLL
Tolerance All AC+DC:± 5 % 3
Icc
MAX_VCCPLL
Max Current for Vcc
PLL
Rail S-Processor Lines — — 150 mA
Notes:
1. Unless otherwise noted, all specifications in this table are based on estimates and simulations or empirical data. These
specifications will be updated with characterized data from silicon measurements at a later date.
2. Long term reliability cannot be assured in conditions above or below Max/Min functional limits.
3. The voltage specification requirements are measured on package pins as near as possible to the processor with an
oscilloscope set to 100-MHz bandwidth, 1.5 pF maximum probe capacitance, and 1 M minimum impedance. The maximum
length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled into the
oscilloscope probe.
Table 7-9. Processor PLL_OC (Vcc
PLL_OC
) Supply DC Voltage and Current Specifications
Symbol Parameter Segment Min Typ Max
Un
it
Notes
1,2
Vcc
PLL_OC
PLL_OC supply
voltage (DC + AC
specification)
All
—V
DDQ
—V 3
TOB
CCPLL_OC
Vcc
PLL_OC
Tolerance All AC+DC:± 5 % 3
Icc
MAX_VCCPLL_OC
Max Current for
Vcc
PLL_OC
Rail
S-Processor Line - Dual Core GT2
S-Processor Line - Quad Core GT2 — —
100
130 mA
Notes:
1. Unless otherwise noted, all specifications in this table are based on estimates and simulations or empirical data. These
specifications will be updated with characterized data from silicon measurements at a later date.
2. Long term reliability cannot be assured in conditions above or below Max/Min functional limits.
3. The voltage specification requirements are measured on package pins as near as possible to the processor with an
oscilloscope set to 100-MHz bandwidth, 1.5 pF maximum probe capacitance, and 1 M minimum impedance. The maximum
length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled into the
oscilloscope probe.