User Guide

Electrical Specifications
118 Datasheet, Volume 1 of 2
7.2.1.4 Vcc
SA
DC Specifications
7.2.1.5 Vcc
IO
DC Specifications
Table 7-5. System Agent (Vcc
SA
) Supply DC Voltage and Current Specifications
Symbol Parameter Segment Min Typ Max Unit Note
1,2
Vcc
SA
Voltage for
the System
Agent
S-Processor Line (fixed voltage) — 1.05 —
V3,5
TOB
VCCSA
Vcc
SA
Tolerance
S-Processor Line
±50(DC+AC+ripple) mV 3
I
CCMAX_VC
CSA
Max Current
for V
CCSA
Rail
-S-Processor Lines — — 11.1
A
T_OVS_M
AX
Max
Overshoot
time
— — — 10
s
V_OVS_M
AX
Max
Overshoot
— — — 70
mV
Notes:
1. Unless otherwise noted, all specifications in this table are based on estimates and simulations or empirical data. These specifications will be
updated with characterized data from silicon measurements at a later date.
2. Long term reliability cannot be assured in conditions above or below Max/Min functional limits.
3. The voltage specification requirements are measured across Vcc
SA
_
SENSE
and Vss
SA
_
SENSE
as near as possible to the processor with an
oscilloscope set to 100-MHz bandwidth, 1.5 pF maximum probe capacitance, and 1 M minimum impedance. The maximum length of
ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled into the oscilloscope probe.
4. PSx refers to the voltage regulator power state as set by the SVID protocol.
5. Vcc
SA
voltage during boot (Vboot)1.05V for a duration of 2 seconds.
6. LL measured at sense points.
7. LL specification values should not be exceeded. If exceeded, power, performance and reliability penalty are expected.
8. N/A
9. N/A
Table 7-6. Processor I/O (Vcc
IO
) Supply DC Voltage and Current Specifications
Symbol Parameter Segment Min Typ Max Unit
Note
1,2
Vcc
IO
Voltage for the memory controller
and shared cache
S
—
0.95
— V 3,4,5,6
TOB
VCCIO
Vcc
IO
Tolerance All AC+DC:± 50 mV 3
Icc
MAX_VCCIO
Max Current for V
CCIO
Rail S — — 5.5 A
T_OVS_MAX Max Overshoot time All — — 100 S7
V_OVS_MAX Max Overshoot at TDP All — — 20 mV 7
Notes:
1. Unless otherwise noted, all specifications in this table are based on estimates and simulations or empirical data. These
specifications will be updated with characterized data from silicon measurements at a later date.
2. Long term reliability cannot be assured in conditions above or below Max/Min functional limits.
3. The voltage specification requirements are measured across Vcc
IO
_
SENSE
and Vss
IO
_
SENSE
as near as possible to the
processor with an oscilloscope set to 100-MHz bandwidth, 1.5 pF maximum probe capacitance, and 1 M minimum
impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the
system is not coupled into the oscilloscope probe.
4. For low BW bus connection between processor and PCH -> Vcc
IO
=0.85V.
5. For high BW bus connection between processor and PCH -> Vcc
IO
=0.95V.
6. N/A
7. OS occurs during power on only, not during normal operation