User Guide

Datasheet, Volume 1 of 2 117
Electrical Specifications
7.2.1.3 V
DDQ
DC Specifications
Notes:
1. Unless otherwise noted, all specifications in this table are based on estimates and simulations or empirical data. These specifications
will be updated with characterized data from silicon measurements at a later date.
2. Each processor is programmed with a maximum valid voltage identification value (VID), which is set at manufacturing and cannot be
altered. Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may
have different settings within the VID range. This differs from the VID employed by the processor during a power or thermal
management event (Intel Adaptive Thermal Monitor, Enhanced Intel SpeedStep Technology, or low-power states).
3. The voltage specification requirements are measured across Vcc
GT
_
SENSE
and Vss
GT
_
SENSE
as near as possible to the processor with
an oscilloscope set to 100-MHz bandwidth, 1.5 pF maximum probe capacitance, and 1 M minimum impedance. The maximum length
of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled into the oscilloscope
probe.
4. PSx refers to the voltage regulator power state as set by the SVID protocol.
5. Each processor is programmed with a maximum valid voltage identification value (VID), which is set at manufacturing and cannot be
altered. Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may
have different settings within the VID range. This differs from the VID employed by the processor during a power or thermal
management event (Intel Adaptive Thermal Monitor, Enhanced Intel SpeedStep Technology, or low-power states).
6. N/A
7. LL measured at sense points.
8. Operating voltage range in steady state.
9. LL specification values should not be exceeded. If exceeded, power, performance and reliability penalty are expected.
10. By Improving Load Line (Lower LL than Datasheet values, and reporting it to BIOS), customers may obtain slightly better
performance although the frequencies will not be changed.
11. N/A
12. For merged GT/GTx rails the sense point need to be taken from Vcc
GT
_SENSE/VSSGT_SENSE, the Vcc
GTx_SENSE
/Vss
GTx_SENSE
should
be unconnected (not connected).
Table 7-4. Memory Controller (V
DDQ
) Supply DC Voltage and Current Specifications
Symbol Parameter Segment Min Typ Max Unit Note
1
V
DDQ (DDR3L/-RS)
Processor I/O supply voltage for
DDR3L/-RS
All
Typ-5% 1.35 Typ+5% V 3,4,5
V
DDQ (DDR4)
Processor I/O supply voltage for
DDR4
All
Typ-5% 1.20 Typ+5% V 3,4,5
TOB
VDDQ
VDDQ Tolerance All AC+DC:± 5 % 3,4
Icc
MAX_VDDQ
(DDR3L/-RS)
Max Current for V
DDQ
Rail
(DDR3L/-RS)
S——2.8
A 2
Icc
MAX_VDDQ
(DDR4)
Max Current for V
DDQ
Rail
(DDR4)
S——2.8
A 2
Notes:
1. Unless otherwise noted, all specifications in this table are based on estimates and simulations or empirical data. These
specifications will be updated with characterized data from silicon measurements at a later date.
2. The current supplied to the DIMM modules is not included in this specification.
3. Includes AC and DC error, where the AC noise is bandwidth limited to under 100 MHz, measured on package pins.
4. No requirement on the breakdown of AC versus DC noise.
5. The voltage specification requirements are measured as near as possible to the processor with an oscilloscope set to 100-MHz
bandwidth, 1.5 pF maximum probe capacitance, and 1 M minimum impedance. The maximum length of ground wire on the
probe should be less than 5 mm. Ensure external noise from the system is not coupled into the oscilloscope probe.
Table 7-3. Processor Graphics (Vcc
GT
) Supply DC Voltage and Current Specifications
(Sheet 2 of 2)
Symbol Parameter Segment Min Typ Max
Unit Note
1