User Guide

Signal Description
106 Datasheet, Volume 1 of 2
6.2 PCI Express* Graphics (PEG) Signals
6.3 Direct Media Interface (DMI) Signals
DDR0_BG[1:0]
DDR1_BG[1:0]
Bank Group: BG[0:1] define to which bank group
an Active, Read, Write or Precharge command is
being applied.
BG0 also determines which mode register is to be
accessed during a MRS cycle.
O DDR4 SE
All processor lines
SO-DIMM, x8 DRAMs,
x16 DDP DRAMs
devices use BG[1:0].
x16 SDP DRAMs
devices use BG[0]
DDR0_BA[1:0]
DDR1_BA[1:0]
Bank Address: BA[1:0] define to which bank an
Active, Read, Write or Precharge command is being
applied. Bank address also determines which mode
register is to be accessed during a MRS cycle.
O DDR4 SE All Processor Lines
DDR0_ALERT#
DDR1_ALERT#
Alert: This signal is used at command training only.
It is getting the Command and Address Parity error
flag during training. CRC feature is not supported.
I DDR4 SE All Processor Lines
DDR0_PAR
DDR1_PAR
Command and Address Parity: These signals are
used for parity check.
O DDR4 SE All Processor Lines
DDR_VREF_CA
Memory Reference Voltage for Command &
Address:
O A SE All Processor Lines
Table 6-4. System Memory Reference and Compensation Signals
Signal Name Description Dir.
Buffer
Type
Link
Type
Availability
DDR_VTT_CNTL
System Memory Power Gate Control: When
signal is high – platform memory VTT regulator is
enable, output high.
When signal is low - Disables the platform memory
VTT regulator in C8 and deeper and S3.
O CMOS SE All Processor Lines
Table 6-5. PCI Express* Interface
Signal Name Description Dir.
Buffer
Type
Link
Type
Availability
PEG_RCOMP
Resistance Compensation for PCI Express
channels PEG and DMI.
N/A A SE
S-Processor Line
PEG_RXP[15:0]
PEG_RXN[15:0]
PCI Express Receive Differential Pairs.
I
PCI
Express*
Diff
PEG_TXP[15:0]
PEG_TXN[15:0]
PCI Express Transmit Differential Pairs.
O
PCI
Express*
Diff
Table 6-6. DMI Interface Signals
Signal Name Description Dir.
Buffer
Type
Link
Type
Availability
DMI_RXP[3:0]
DMI_RXN[3:0]
DMI Input from PCH: Direct Media
Interface receive differential pairs.
IDMIDiff
S-Processor Line
DMI_TXP[3:0]
DMI_TXN[3:0]
DMI Output to PCH: Direct Media Interface
transmit differential pairs.
ODMIDiff
Table 6-3. DDR4 Memory Interface (Sheet 2 of 2)
Signal Name Description Dir.
Buffer
Type
Link
Type
Availability