User Guide

Datasheet, Volume 1 of 2 105
Signal Description
Table 6-3. DDR4 Memory Interface (Sheet 1 of 2)
Signal Name Description Dir.
Buffer
Type
Link
Type
Availability
DDR0_DQ[63:0]
DDR1_DQ[63:0]
Data Buses: Data signals interface to the SDRAM
data buses.
I/O DDR4 SE All Processor Lines
DDR0_DQSP[7:0]
DDR0_DQSN[7:0]
DDR1_DQSP[7:0]
DDR1_DQSN[7:0]
Data Strobes: Differential data strobe pairs. The
data is captured at the crossing point of DQS during
read and write transactions.
I/O DDR4 Diff All Processor Lines
DDR0_CKN[3:0]
DDR0_CKP[3:0]
DDR1_CKN[3:0]
DDR1_CKP[3:0]
SDRAM Differential Clock: Differential clocks
signal pairs, pair per rank. The crossing of the
positive edge of DDR0_CKP/DDR1_CKP and the
negative edge of their complement DDR0_CKN /
DDR1_CKN are used to sample the command and
control signals on the SDRAM.
O DDR4 Diff
[1:0] applicable for All
Processor Lines.
[3:2] applicable only
in S-Processor Line
processors
DDR0_CKE[3:0]
DDR1_CKE[3:0]
Clock Enable: (1 per rank). These signals are used
to:
• Initialize the SDRAMs during power-up.
• Power-down SDRAM ranks.
• Place all SDRAM ranks into and out of self-
refresh during STR (Suspend to RAM).
O DDR4 SE
[1:0] applicable for All
Processor Lines.
[3:2] applicable only
in S-Processor Line
processors.
DDR0_CS#[3:0]
DDR1_CS#[3:0]
Chip Select: (1 per rank). These signals are used
to select particular SDRAM components during the
active state. There is one Chip Select for each
SDRAM rank.
O DDR4 SE
[1:0] applicable for All
Processor Lines.
[3:2] applicable only
in S-Processor Line
processors
DDR0_ODT[3:0]
DDR1_ODT[3:0]
On Die Termination: (1 per rank). Active SDRAM
Termination Control.
O DDR4 SE
[0] applicable for All
Processor Lines.
[1] applicable for S-
Processor Lines.
[3:2] applicable only
in S-Processor Line
processors
DDR0_MA[16:0]
DDR1_MA[16:0]
Address: These signals are used to provide the
multiplexed row and column address to the SDRAM.
• A[16:14] use also as command signals, see
ACT# signal description.
• A10 is sampled during Read/Write commands
to determine whether Autoprecharge should be
performed to the accessed bank after the
Read/Write operation.
HIGH: Autoprecharge;
LOW: no Autoprecharge).
• A10 is sampled during a Precharge command
to determine whether the Precharge applies to
one bank (A10 LOW) or all banks (A10 HIGH).
If only one bank is to be precharged, the bank
is selected by bank addresses.
• A12 is sampled during Read and Write
commands to determine if burst chop (on-the-
fly) will be performed.
HIGH, no burst chop;
LOW: burst chopped).
O DDR4 SE All Processor Lines
DDR0_ACT#
DDR1_ACT#
Activation Command: ACT# HIGH along with
CS# determines that the signals addresses below
have command functionality.
A16 use as RAS# signal
A15 use as CAS# signal
A14 use as WE# signal
O DDR4 SE All Processor Lines