User Guide

Signal Description
104 Datasheet, Volume 1 of 2
DDR0_CKE
DDR1_CKE
Clock Enable: (1 per rank). These signals are used
to:
• Initialize the SDRAMs during power-up.
• Power-down SDRAM ranks.
• Place all SDRAM ranks into and out of self-
refresh during STR (Suspend to RAM).
O DDR3L SE
[1:0] applicable for all
Processor Lines.
[3:2] applicable only in
S-Processor Line
processors.
DDR0_CS#
DDR1_CS#
Chip Select: (1 per rank). These signals are used
to select particular SDRAM components during the
active state. There is one Chip Select for each
SDRAM rank.
O DDR3L SE
[1:0] applicable for all
Processor Lines.
[3:2] applicable only in
S-Processor Line
processors
DDR0_ODT
DDR1_ODT
On Die Termination: (1 per rank). Active SDRAM
Termination Control.
O DDR3L SE
[0] applicable for all
Processor Lines.
[1] applicable for S-
Processor Lines.
[3:2] applicable only in
S-Processor Line
processors
DDR0_MA[15:0]
DDR1_MA[15:0]
Memory Address: These signals are used to
provide the multiplexed row and column address to
the SDRAM.
• A10 is sampled during Read/Write commands
to determine whether Autoprecharge should be
performed to the accessed bank after the
Read/Write operation.
HIGH: Autoprecharge;
LOW: no Autoprecharge.
• A10 is sampled during a Precharge command
to determine whether the Precharge applies to
one bank (A10 LOW) or all banks (A10 HIGH).
If only one bank is to be precharged, the bank
is selected by bank addresses.
• A12 is sampled during Read and Write
commands to determine if burst chop (on-the-
fly) will be performed.
HIGH: no burst chop;
LOW: burst chopped.
O DDR3L SE All Processor Lines
DDR0_BA[2:0]
DDR1_BA[2:0]
Bank Select: These signals define which banks are
selected within each SDRAM rank.
O DDR3L SE All Processor Lines
DDR0_CAS#
DDR1_CAS#
CAS Control Signal: Column Address Select
command signal
O DDR3L SE All Processor Lines
DDR0_RAS#
DDR1_RAS#
RAS Control Signal: Row Address Select
command signal
O DDR3L SE All Processor Lines
DDR0_WE#
DDR1_WE#
WE Control Signal: Write Enable command signal
O DDR3L SE All Processor Lines
DDR0_VREF_DQ
DDR1_VREF_DQ
Memory Reference Voltage for DQ:
O A SE All Processor Lines
DDR_VREF_CA
Memory Reference Voltage for Command &
Address:
O A SE All Processor Lines
Table 6-2. DDR3L/-RS Memory Interface (Sheet 2 of 2)
Signal Name Description Dir.
Buffer
Type
Link
Type
Availability