7th Generation Intel® Processor Families for S Platforms Datasheet, Volume 1 of 2 Supporting 7th Generation Intel® Core™ Processor Families, Intel® Pentium® Processors, Intel® Celeron® Processors for S Platforms Document Number:335195-001
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Contents 1 Introduction ............................................................................................................ 11 1.1 Supported Technologies ..................................................................................... 13 1.2 Power Management Support ............................................................................... 13 1.2.1 Processor Core Power Management........................................................... 13 1.2.2 System Power Management .................
2.5 2.6 2.4.8 GT2 Graphic Frequency ...........................................................................35 Display Interfaces ..............................................................................................36 2.5.1 DisplayPort* ..........................................................................................39 2.5.2 High-Definition Multimedia Interface (HDMI*).............................................40 2.5.3 Digital Video Interface (DVI) ..................................
4.3.1 4.3.2 4.4 4.5 4.6 4.7 5 Disabling Unused System Memory Outputs ................................................ 73 DRAM Power Management and Initialization ............................................... 73 4.3.2.1 Initialization Role of CKE ............................................................ 74 4.3.2.2 Conditional Self-Refresh ............................................................ 74 4.3.2.3 Dynamic Power-Down................................................................ 75 4.3.2.
5.2.1.3 5.2.1.4 5.2.1.5 5.2.1.6 5.2.1.7 Thermal Profile for PCG 2015B Processor ......................................97 Thermal Profile for PCG 2015A Processor ......................................98 Thermal Metrology ....................................................................99 Fan Speed Control Scheme with Digital Thermal Sensor (DTS) 1.1 ...99 Fan Speed Control Scheme with Digital Thermal Sensor (DTS) 2.0 . 101 6 Signal Description ...........................................................
Figures 1-1 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 3-1 4-1 4-2 4-3 4-4 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 7-1 S-Processor Line Platforms ...................................................................................... 12 Intel® Flex Memory Technology Operations ............................................................... 23 Interleave (IL) and Non-Interleave (NIL) Modes Mapping............................................. 25 PCI Express* Related Register Structures in the Processor ................
2-24 2-25 2-26 2-27 2-28 2-29 2-30 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 5-11 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 6-10 6-11 6-12 6-13 6-14 6-15 6-16 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 7-10 7-11 7-12 8 S-Processor Line Display Resolution Configuration (DP@30 Hz) ....................................43 HDCP Display supported Implications Table ................................................................44 Display Link Data Rate Support .............................
7-13 7-14 7-15 7-16 7-17 8-1 8-2 Digital Display Interface Group DC Specifications (DP/HDMI)...................................... 122 embedded DisplayPort* (eDP*) Group DC Specifications............................................ 122 CMOS Signal Group DC Specifications ..................................................................... 123 GTL Signal Group and Open Drain Signal Group DC Specifications............................... 123 PECI DC Electrical Limits .........................................
Revision History Revision Number 001 Description • Initial release Revision Date January 2017 §§ 10 Datasheet, Volume 1 of 2
Introduction 1 Introduction The 7th Generation Intel® Core™ processor, Intel® Pentium® processor, Intel® Celeron® processor families are 64-bit, multi-core processors built on 14-nanometer process technology. The S-Processor Line processors are offered in a 2-Chip Platform. The S-Processor Line is connected to a discrete Intel® 200 Series Series Chipset Family Platform Controller Hub (PCH). See the following figure. The following table describes the processor lines covered in this document. Table 1-1.
Introduction Figure 1-1. S-Processor Line Platforms PCI Express* 3.0 x 16 DDR Ch. A Digital Display Interface x 3 DDIx3 embedded DisplayPort* eDP* Cameras Touch Screen Fingerprint Sensor USB 2.0 DDR Ch. B PECI EC SMBus DMI 3.0 BIOS/FW Flash SPI/ I2C/ USB2 eSPI / LPC USB 2.0 PTT USB 2.0/3.0/3.1 PCH SATA Gigabit Network Connection SMBus 2.0 BT/3G/4G SDIO USB 2.0/3.0/3.1 Ports SSD Drive HDA/I2S USB 2.0 PCI Express* 3.
Introduction 1.1 Supported Technologies • Intel® Virtualization Technology (Intel® VT) • Intel® Active Management Technology 11.0 (Intel® AMT 11.0) • Intel® Trusted Execution Technology (Intel® TXT) • Intel® Streaming SIMD Extensions 4.2 (Intel® SSE4.2) • Intel® Hyper-Threading Technology (Intel® HT Technology) • Intel® 64 Architecture • Execute Disable Bit • Intel® Turbo Boost Technology 2.
Introduction 1.2.3 Memory Controller Power Management • Disabling Unused System Memory Outputs • DRAM Power Management and Initialization • Initialization Role of CKE • Conditional Self-Refresh • Dynamic Power Down • DRAM I/O Power Management • DDR Electrical Power Gating (EPG) • Power training Refer to Section 4.3 for more information. 1.2.4 Processor Graphics Power Management 1.2.4.
Introduction • External Thermal Sensor (TS-on-DIMM and TS-on-Board) • Render Thermal Throttling • Fan speed control with DTS • Intel Turbo Boost Technology 2.0 Power Control Refer to Chapter 5, “Thermal Management” for more information. 1.4 Package Support The processor is available in the following packages: • A 37.5 mm x 37.5 mm LGA package (LGA1151) for S-Processor Line 1.5 Processor Testability An XDP on-board connector is warmly recommended to enable full debug capabilities.
Introduction Table 1-2.
Introduction Table 1-2. Terminology (Sheet 3 of 3) Term Description Processor Core The term “processor core” refers to Si die itself, which can contain multiple execution cores. Each execution core has an instruction cache, data cache, and 256KB L2 cache. All execution cores share the LLC. Processor Graphics Intel Processor Graphics PSR Panel Self-Refresh Rank A unit of DRAM corresponding to four to eight devices in parallel, ignoring ECC.
Introduction Table 1-3. Related Documents (Sheet 2 of 2) Document Document Number / Location 200 Series Chipset Family Platform Controller Hub (PCH) Datasheet Volume 2 of 2 335193 Intel® 200 Series Chipset Family Platform Controller Hub (PCH) Specification Update 335194 Intel® Advanced Configuration and Power Interface 3.0 http://www.acpi.info/ DDR3L SDRAM Specification http://www.jedec.org DDR4 Specification http://www.jedec.org High Definition Multimedia Interface specification revision 1.
Interfaces 2 Interfaces 2.1 System Memory Interface • Two channels of DDR3L/-RS, and DDR4 memory with a maximum of two DIMMs per channel. DDR technologies, number of DIMMs per channel, number of ranks per channel are SKU dependent. • UDIMM, SO-DIMM, and Memory Down support (based on SKU) • Single-channel and dual-channel memory organization modes • Data burst length of eight for all memory organization modes • DDR3L/-RS I/O Voltage of 1.35V - based on Processor Line • DDR4 I/O Voltage of 1.
Interfaces • DDR3L/-RS Data Transfer Rates: — 1333 MT/s (PC3-10600) — 1600 MT/s (PC3-12800) • DDR4 Data Transfer Rates: — 2133 MT/s (PC4-2133) — 2400 MT/s (PC4-2400) • SODIMM Modules: DDR3L/-RS SODIMM/UDIMM Modules: — Standard 4-Gb technology and addressing are supported for x8 and x16 devices. DDR4 SODIMM/UDIMM Modules: — Standard 4-Gb and 8-Gb technologies and addressing are supported for x8 and x16 devices.
Interfaces 2.1.1.2 DDR4 Supported Memory Modules and Devices Table 2-5. Supported DDR4 Non-ECC UDIMM Module Configurations (S-Processor Lines) Table 2-6. Table 2-7. Table 2-8.
Interfaces Table 2-8. 2.1.
Interfaces address of the channel with the smaller capacity is reached. In this mode, the system runs with one zone of dual-channel mode and one zone of single-channel mode, simultaneously, across the whole memory array. Note: Channels A and B can be mapped for physical channel 0 and 1 respectively or vice versa. However, channel A size should be greater or equal to channel B size. Figure 2-1.
Interfaces BIOS will use the slower of the two latencies for both channels. For Dual-Channel modes both channels should have a DIMM connector populated. For Single-Channel mode, only a single channel can have a DIMM connector populated. 2.1.5 Technology Enhancements of Intel® Fast Memory Access (Intel® FMA) The following sections describe the Just-in-Time Scheduling, Command Overlap, and Out-of-Order Scheduling Intel FMA technology enhancements.
Interfaces • Interleave (IL) • Non-Interleave (NIL) The following table and figure describe the pin mapping between the IL and NIL modes. Table 2-10. Interleave (IL) and Non-Interleave (NIL) Modes Pin Mapping IL Figure 2-2.
Interfaces 2.1.8 Data Swapping By default, the processor supports on-board data swapping in two manners (for all segments and DRAM technologies): • byte (DQ+DQS) swapping between bytes in the same channel. • bit swapping within specific byte. 2.1.9 DRAM Clock Generation Every supported rank has a differential clock pair. There are a total of four clock pairs driven directly by the processor to DRAM. 2.1.
Interfaces Table 2-11.
Interfaces • Power Management Event (PME) functions • Dynamic width capability • Message Signaled Interrupt (MSI and MSI-X) messages • Lane reversal The following table summarizes the transfer rates and theoretical bandwidth of PCI Express* link. Table 2-12. PCI Express* Maximum Transfer Rates and Theoretical Bandwidth PCI Express* Generation Encoding Theoretical Bandwidth [GB/s] Maximum Transfer Rate [GT/s] x1 x2 x4 x8 x16 Gen 1 8b/10b 2.5 0.25 0.5 1.0 2.0 4.0 Gen 2 8b/10b 5 0.5 1.
Interfaces 2.2.3 PCI Express* Configuration Mechanism The PCI Express* (external graphics) link is mapped through a PCI-to-PCI bridge structure. Figure 2-3. PCI Express* Related Register Structures in the Processor PCI Express* Device PEG PCI-PCI Bridge representing root PCI Express* ports (Device 1) PCI Compatible Host Bridge Device (Device 0) DMI PCI Express* extends the configuration space to 4096 bytes per-device/function, as compared to 256 bytes allowed by the conventional PCI specification.
Interfaces • Full RX Equalization and acquisition for: AGC (Adaptive Gain Control), CDR (Clock and Data Recovery), adaptive DFE (decision feedback equalizer) and adaptive CTLE peaking (continuous time linear equalizer). • Full adaptive phase 3 EQ compliant with PCI Express* Gen 3 specification See the PCI Express* Base Specification 3.0 for details on PCI Express* equalization. 2.3 Direct Media Interface (DMI) Direct Media Interface (DMI) connects the processor and the PCH.
Interfaces Multi-format HW assisted decode/encode pipeline, and Mid-Level Cache (MLC) for superior high definition playback, video quality, and improved 3D performance and media. The Display Engine handles delivering the pixels to the screen. GSA (Graphics in System Agent) is the primary channel interface for display memory accesses and PCIlike traffic in and out. The display engine supports the latest display standards such as eDP* 1.4, DP* 1.2, HDMI* 1.
Interfaces • MFT (Media Foundation Transform) filters. Gen 9 LP supports full HW accelerated video decoding for AVC/VC1/MPEG2/HEVC/VP8/ JPEG. Table 2-13. Hardware Accelerated Video Decoding Codec Profile Level Maximum Resolution Main Main High 1080p VC1/WMV9 Advanced Main Simple L3 High Simple 3840x3840 AVC/H264 High Main MVC & stereo L5.1 2160p(4K) MPEG2 VP8 0 Unified level 1080p Baseline Unified level 16k x16k Main L5.1 2160(4K) Main BT2020, isolate Dec L5.
Interfaces Note: Hardware encode for H264 SVC is not supported. 2.4.3.
Interfaces 2.4.5 Switchable/Hybrid Graphics The processor supports Switchable/Hybrid graphics. Switchable graphics: The Switchable Graphics feature allows you to switch between using the Intel integrated graphics and a discrete graphics card. The Intel Integrated Graphics driver will control the switching between the modes. In most cases it will operate as follows: when connected to AC power - Discrete graphic card; when connected to DC (battery) - Intel integrated GFX.
Interfaces 2.4.7 Gen 9 LP (9th Generation Low Power) Block Diagram Figure 2-5.
Interfaces 2.5 Display Interfaces The processor supports single eDP* interface and 3 DDI interfaces (depends on segment): • DDI interface can be configured as DisplayPort* or HDMI*. • Each DDI can support dual mode (DP++). • Each DDI can support DVI (DVI max resolution is 1920x1200 @ 60 Hz). • The DisplayPort* can be configured to use 1, 2, or 4 lanes depending on the bandwidth requirements and link data rate. • DDI ports notated as: DDI B, C, D.
Interfaces Table 2-19. Display Technologies Support Technology Standard eDP* 1.4 VESA* Embedded DisplayPort* Standard 1.4 DisplayPort* 1.2 VESA DisplayPort* Standard 1.2 VESA DisplayPort* PHY Compliance Test Specification 1.2 VESA DisplayPort* Link Layer Compliance Test Specification 1.2 HDMI* 1.41 High-Definition Multimedia Interface Specification Version 1.4 Notes: 1. HDMI* 2.0/2.0a support is possible using LS-Pcon converter chip connected to the DP port. The LS-Pcon supports 2 modes: a.
Interfaces Table 2-20. Display Resolutions and Link Bandwidth for Multi-Stream Transport Calculations (Sheet 2 of 2) Pixels per line Lines Refresh Rate [Hz] Pixel Clock [MHz] Link Bandwidth [Gbps] 2880 1800 60 337.5 10.13 3200 2400 60 497.75 14.93 3840 2160 60 533.25 16.00 4096 2160 60 556.75 17.02 4096 2304 60 605 18.15 Notes: 1. All above is related to bit depth of 24. 2. The data rate for a given video mode can be calculated as: Data Rate = Pixel Frequency * Bit Depth. 3.
Interfaces Figure 2-6.
Interfaces The processor is designed in accordance to VESA* DisplayPort* specification. Refer to Table 2-19, “Display Technologies Support”. Figure 2-7. DisplayPort* Overview Source Device DisplayPort Tx (Processor) Main Link (Isochronous Streams) Sink Device DisplayPort Rx AUX CH (Link/Device Managemet) Hot‐Plug Detect (Interrupt Request) 2.5.
Interfaces Figure 2-8. HDMI* Overview HDMI Sink HDMI Source HDMI Tx (Processor) TMDS Data Channel 0 HDMI Rx TMDS Data Channel 1 TMDS Data Channel 2 TMDS Clock Channel Hot‐Plug Detect Display Data Channel (DDC) CEC Line (optional) 2.5.3 Digital Video Interface (DVI) The processor Digital Ports can be configured to drive DVI-D. DVI uses TMDS for transmitting data from the transmitter to the receiver, which is similar to the HDMI protocol except for the audio and CEC.
Interfaces Table 2-21. Processor Supported Audio Formats over HDMI and DisplayPort* Audio Formats HDMI* DisplayPort* AC-3 Dolby* Digital Yes Yes Dolby Digital Plus Yes Yes DTS-HD* Yes Yes LPCM, 192 kHz/24 bit, 8 Channel Yes Yes Dolby TrueHD, DTS-HD Master Audio* (Lossless Blu-Ray Disc* Audio Format) Yes Yes The processor will continue to support Silent stream.
Interfaces Table 2-22. Maximum Display Resolution (Sheet 2 of 2) Standard S-Processor Line Notes Notes: 1. Maximum resolution is based on implementation of 4 lanes with HBR2 link data rate. 2. bpp - bit per pixel. 3. Supports up to 4 displays, but only three can be active at the same time. 4. N/A 5. In the case of connecting more than one active display port, the processor frequency may be lower than base frequency at thermally limited scenario. 6. HDMI2.0 implemented using LSPCON device.
Interfaces Some minor difference will be between Integrated HDCP2.2 over HDMI1.4 compared to the HDCP2.2 over LSPCON in HDMI1.4 Mode. Also, LSPCON is needed for HDMI 2.0a which defines HDR over HDMI. The HDCP 1.4 keys are integrated into the processor and customers are not required to physically configure or handle the keys. Table 2-25. HDCP Display supported Implications Table Topic DP HDMI1.4 HDCP Revision Maximum Resolution HDR1 HDCP Solution2 BPC3 HDCP1.4 4K@60 No iHDCP 10 bit HDCP2.
Interfaces Table 2-27. Display Resolution and Link Rate Support (Sheet 2 of 2) 2.5.10 Table 2-28. Resolution Link Rate Support High Definition 3200x1800 5.4 (HBR2) QHD+ 2880x1800 2.7 (HBR) QHD 2880x1620 2.7 (HBR) QHD 2560x1600 2.7 (HBR) QHD 2560x1440 2.7 (HBR) QHD 1920x1080 1.62 (RBR) FHD Display Bit Per Pixel (BPP) Support Display Bit Per Pixel (BPP) Support Technology eDP* 24,30,36 DisplayPort* 24,30,36 HDMI* 2.5.11 Table 2-29.
Interfaces memory throttling control mechanisms and many other services. PECI is used for platform thermal management and real time control and configuration of processor features and performance. 2.6.1 PECI Bus Architecture The PECI architecture is based on a wired OR bus that the clients (as processor PECI) can pull up (with strong drive). The idle state on the bus is near zero.
Interfaces Figure 2-10.
Technologies 3 Technologies This chapter provides a high-level description of Intel technologies implemented in the processor. The implementation of the features may vary between the processor SKUs. Details on the different technologies of Intel processors and other relevant external notes are located at the Intel technology web site: http://www.intel.com/technology/ 3.
Technologies • More secure: The use of hardware transitions in the VMM strengthens the isolation of VMs and further prevents corruption of one VM from affecting others on the same system.
Technologies to translate the linear address), the resulting guest-physical address is executable under EPT only if the XS bit is set in every EPT pagingstructure entry used to translate the guest-physical address —The XU and XS bits are used only when translating linear addresses for guest code fetches.
Technologies • DMA remapping: for supporting independent address translations for Direct Memory Accesses (DMA) from devices. • Interrupt remapping: for supporting isolation and routing of interrupts from devices and external interrupt controllers to appropriate VMs. • Reliability: for recording and reporting to system software DMA and interrupt errors that may otherwise corrupt memory or impact VM isolation.
Technologies Intel VT-d functionality, often referred to as an Intel VT-d Engine, has typically been implemented at or near a PCI Express* host bridge component of a computer system. This might be in a chipset component or in the PCI Express functionality of a processor with integrated I/O. When one such VT-d engine receives a PCI Express transaction from a PCI Express bus, it uses the B/D/F number associated with the transaction to search for an Intel VT-d translation table.
Technologies • Intel VT-d superpage – support of Intel VT-d superpage (2 MB, 1 GB) for default Intel VT-d engine (that covers all devices except IGD) IGD Intel VT-d engine does not support superpage and BIOS should disable superpage in default Intel VT-d engine when iGfx is enabled. Note: Intel VT-d Technology may not be available on all SKUs. 3.2 Security Technologies 3.2.
Technologies For the above features, BIOS should test the associated capability bit before attempting to access any of the above registers. For more information, refer to the Intel® Trusted Execution Technology Measured Launched Environment Programming Guide Note: Intel TXT Technology may not be available on all SKUs. 3.2.
Technologies 3.2.5 Execute Disable Bit The Execute Disable Bit allows memory to be marked as non executable when combined with a supporting operating system. If code attempts to run in nonexecutable memory, the processor raises an error to the operating system. This feature can prevent some classes of viruses or worms that exploit buffer overrun vulnerabilities and can, thus, help improve the overall security of the system.
Technologies 3.2.9 Intel® Memory Protection Extensions (Intel® MPX) Intel® MPX provides hardware accelerated mechanism for memory testing (heap and stack) buffer boundaries in order to identify buffer overflow attacks. An Intel MPX enabled compiler inserts new instructions that tests memory boundaries prior to a buffer access. Other Intel MPX commands are used to modify a database of memory regions used by the boundary checker instructions.
Technologies 3.2.11 Intel® Virtualization Technology (Intel® VT) for Directed I/O (Intel® VT-d) Refer to Section 3.1.2 Intel VT-d for detail. 3.3 Power and Performance Technologies 3.3.1 Intel® Hyper-Threading Technology (Intel® HT Technology) The processor supports Intel® Hyper-Threading Technology (Intel® HT Technology) that allows an execution processor IA core to function as two logical processors.
Technologies active if the operating system is requesting the P0 state. If turbo frequencies are limited the cause is logged in IA_PERF_LIMIT_REASONS register. For more information on P-states and C-states, see Power Management. 3.3.3 Intel® Advanced Vector Extensions 2 (Intel® AVX2) Intel® Advanced Vector Extensions 2.0 (Intel® AVX2) is the latest expansion of the Intel instruction set.
Technologies The key enhancements provided by the x2APIC architecture over xAPIC are the following: • Support for two modes of operation to provide backward compatibility and extensibility for future platform innovations: — In xAPIC compatibility mode, APIC registers are accessed through memory mapped interface to a 4K-Byte page, identical to the xAPIC architecture. — In x2APIC mode, APIC registers are accessed through Model Specific Register (MSR) interfaces.
Technologies 3.3.6 Intel® Transactional Synchronization Extensions (Intel® TSX-NI) Intel® Transactional Synchronization Extensions (Intel® TSX-NI) provides a set of instruction set extensions that allow programmers to specify regions of code for transactional synchronization. Programmers can use these extensions to achieve the performance of fine-grain locking while actually programming using coarse-grain locks.
Power Management 4 Power Management This chapter provides information on the following power management topics: • Advanced Configuration and Power Interface (ACPI) States • Processor IA Core Power Management • Integrated Memory Controller (IMC) Power Management • PCI Express* Power Management • Direct Media Interface (DMI) Power Management • Processor Graphics Power Management Datasheet, Volume 1 of 2 61
Power Management Figure 4-1. Processor Power States G0 – Working S0 – Processor powered on C0 – Active mode P0 Pn C1 – Auto halt C1E – Auto halt, low frequency, low voltage C2 – Temporary state before C3 or deeper.
Power Management Processor Package and IA Core C-States PACKAGE STATE Figure 4-2.
Power Management Table 4-2. Processor IA Core / Package State Support State C0 Table 4-3. Description Active mode, processor executing code. C1 AutoHALT processor IA core state (package C0 state). C1E AutoHALT processor IA core state with lowest frequency and voltage operating point (package C0 state). C2 All processor IA cores in C3 or deeper. Memory path open. Temporary state before Package C3 or deeper.
Power Management Table 4-6. 4.
Power Management 4.2.1.2 Intel® Speed Shift Technology Intel Speed Shift Technology is an energy efficient method of frequency control by the hardware rather than relying on OS control. OS is aware of available hardware P-states and request a desired P-state or it can let Hardware determine the P-state. The OS request is based on its workload requirements and awareness of processor capabilities.
Power Management 4.2.3 Requesting Low-Power Idle States The primary software interfaces for requesting low-power idle states are through the MWAIT instruction with sub-state hints and the HLT instruction (for C1 and C1E). However, software may make C-state requests using the legacy method of I/O reads from the ACPI-defined processor clock control registers, referred to as P_LVLx.
Power Management A System Management Interrupt (SMI) handler returns execution to either Normal state or the C1/C1E state. See the Intel 64 and IA-32 Architectures Software Developer’s Manual for more information. While a processor IA core is in C1/C1E state, it processes bus snoops and snoops from other threads. For more information on C1E, see Section 4.2.5.
Power Management This feature is disabled by default. BIOS should enable it in the PMG_CST_CONFIG_CONTROL register. The auto-demotion policy is also configured by this register. 4.2.5 Package C-States The processor supports C0, C2, C3, C6, C7, C8 package states. The following is a summary of the general rules for package C-state entry.
Power Management Figure 4-4. Package C-State Entry and Exit Package C0 Package C2 Package C3 Package C6 Package C7 Package C8 Package C0 This is the normal operating state for the processor. The processor remains in the normal state when at least one of its processor IA cores is in the C0 or C1 state or when the platform has not granted permission to the processor to go into a low-power state. Individual processor IA cores may be in deeper power idle states while the package is in C0 state.
Power Management In package C3-state, the LLC shared cache is valid. Package C6 State A processor enters the package C6 low-power state when: • At least one processor IA core is in the C6 state. • The other processor IA cores are in a C6 or deeper power state, and the processor has been granted permission by the platform. • The platform has not granted a package C7 or deeper request but has allowed a C6 package state.
Power Management • Single or multiple displays • Native or non-native resolution • Panel Self Refresh (PSR) technology Note: Display resolution is not the only factor influencing the deepest Package C-state the processor can get into. Device latencies, interrupt response latencies, and core Cstates are among other factors that influence the final package C-state the processor can enter. The following table lists display resolutions and deepest available package C-State.
Power Management 4.3 Integrated Memory Controller (IMC) Power Management The main memory is power managed during normal operation and in low-power ACPI C-states. 4.3.1 Disabling Unused System Memory Outputs Any system memory (SM) interface signal that goes to a memory in which it is not connected to any actual memory devices (such as SODIMM connector is unpopulated, or is single-sided) is tri-stated. The benefits of disabling unused SM signals are: • Reduced power consumption.
Power Management better than APD, but less than DLL-off. Power consumption is defined by IDD2P. Exiting this mode is defined by tXP. The difference from APD mode is that when waking-up, all page-buffers are empty.) The LPDDR does not have a DLL. As a result, the power savings are as good as PPD/DDL-off but will have lower exit latency and higher performance. The CKE is determined per rank, whenever it is inactive. Each rank has an idle counter.
Power Management When entering the S3 – Suspend-to-RAM (STR) state or S0 conditional self-refresh, the processor IA core flushes pending cycles and then enters SDRAM ranks that are not used by the processor graphics into self-refresh. The CKE signals remain LOW so the SDRAM devices perform self-refresh. The target behavior is to enter self-refresh for package C3 or deeper power states as long as there are no memory requests to service. Table 4-8. Targeted Memory State Conditions State 4.3.2.
Power Management In C7 or deeper power state, the processor internally gates VCCIO for all non-critical state to reduce idle power. In S3 or C-state transitions, the DDR does not go through training mode and will restore the previous training information. 4.3.4 Power Training BIOS MRC performing Power Training steps to reduce DDR I/O power while keeping reasonable operational margins, still ensuring platform operation.
Power Management 4.6 Processor Graphics Power Management 4.6.1 Memory Power Savings Technologies 4.6.1.1 Intel® Rapid Memory Power Management (Intel® RMPM) Intel® Rapid Memory Power Management (Intel® RMPM) conditionally places memory into self-refresh when the processor is in package C3 or deeper power state to allow the system to remain in the deeper power states longer for memory not reserved for graphics memory.
Power Management 4.6.2.3 Smooth Brightness The Smooth Brightness feature is the ability to make fine grained changes to the screen brightness. All Windows* 10 system that support brightness control are required to support Smooth Brightness control and it should be supporting 101 levels of brightness control. Apart from the Graphics driver changes, there may be few System BIOS changes required to make this feature functional. 4.6.2.4 Intel® Display Power Saving Technology (Intel® DPST) 6.
Power Management 4.6.3 Processor Graphics Core Power Savings Technologies 4.6.3.1 Intel® Graphics Dynamic Frequency Intel Turbo Boost Technology 2.0 is the ability of the processor IA cores and graphics (Graphics Dynamic Frequency) cores to opportunistically increase frequency and/or voltage above the guaranteed processor and graphics frequency for the given part.
Thermal Management 5 Thermal Management 5.1 Processor Thermal Management The thermal solution provides both component-level and system-level thermal management. To allow optimal operation and long-term reliability of Intel processorbased systems, the system/processor thermal solution should be designed so that the processor: • Bare Die Parts: Remains below the maximum junction temperature (TjMAX) specification at the maximum thermal design power (TDP).
Thermal Management • The processor may exceed the TDP for short durations to utilize any available thermal capacitance within the thermal solution. The duration and time of such operation can be limited by platform runtime configurable registers within the processor. • Graphics peak frequency operation is based on the assumption of only one of the graphics domains (GT/GTx) being active.
Thermal Management Note: Implementation of Intel Turbo Boost Technology 2.0 only requires configuring PL1, PL1 Tau, and PL2. Note: PL3 and PL4 are disabled by default. Figure 5-1. Package Power Control 5.1.3.2 Platform Power Control The processor supports Psys (Platform Power) to enhance processor power management. The Psys signal needs to be sourced from a compatible charger circuit and routed to the IMVP8 (voltage regulator).
Thermal Management • The Psys signal and associated power limits / Tau are optional for the system designer and disabled by default. • The Psys data will not include power consumption for charging. 5.1.3.3 Turbo Time Parameter (Tau) Turbo Time Parameter (Tau) is a mathematical parameter (units of seconds) that controls the Intel Turbo Boost Technology 2.0 algorithm. During a maximum power turbo event, the processor could sustain PL2 for a duration longer than the Turbo Time Parameter.
Thermal Management Table 5-1. Configurable TDP Modes (Sheet 2 of 2) Mode Description TDP-Up The SKU-specific processor IA core frequency where manufacturing confirms logical functionality within the set of operating condition limits specified for the SKU segment and Configurable TDP-Up configuration in Table 5-2, Table 5-3 and Table 5-5. The Configurable TDP-Up Frequency and corresponding TDP is higher than the processor IA core Base Frequency and SKU Segment Base TDP.
Thermal Management active as long as the package temperature remains at its specified limit. Therefore, the Adaptive Thermal Monitor will continue to reduce the package frequency and voltage until the TCC is de-activated. TjMAX is factory calibrated and is not user configurable. The default value is software visible in the TEMPERATURE_TARGET (0x1A2) MSR, bits [23:16]. The Adaptive Thermal Monitor does not require any additional hardware, software drivers, or interrupt handling routines.
Thermal Management 5.1.5.1.2 Frequency / Voltage Control Upon Adaptive Thermal Monitor activation, the processor attempts to dynamically reduce processor temperature by lowering the frequency and voltage operating point. The operating points are automatically calculated by the processor IA core itself and do not require the BIOS to program them as with previous generations of Intel processors.
Thermal Management 5.1.5.2 Digital Thermal Sensor Each processor has multiple on-die Digital Thermal Sensor (DTS) that detects the processor IA, GT and other areas of interest instantaneous temperature. Temperature values from the DTS can be retrieved through: • A software interface using processor Model Specific Register (MSR). • A processor hardware interface as described in Platform Environmental Control Interface (PECI).
Thermal Management 5.1.5.4 Bi-Directional PROCHOT# By default, the PROCHOT# signal is set to input only. When configured as an input or bi-directional signal, PROCHOT# can be used for thermally protecting other platform components should they overheat as well. When PROCHOT# is driven by an external device: • The package will immediately transition to the lowest P-State (Pn) supported by the processor IA cores and graphics cores.
Thermal Management 5.1.5.7 Low-Power States and PROCHOT# Behavior Depending on package power levels during package C-states, outbound PROCHOT# may de-assert while the processor is idle as power is removed from the signal. Upon wake up, if the processor is still hot, the PROCHOT# will re-assert. Although, typically package idle state residency should resolve any thermal issues.
Thermal Management 5.1.5.12 I/O Emulation-Based On-Demand Mode I/O emulation-based clock modulation provides legacy support for operating system software that initiates clock modulation through I/O writes to ACPI defined processor clock control registers on the chipset (PROC_CNT). Thermal throttling using this method will modulate all processor IA cores simultaneously. 5.1.
Thermal Management 5.2 Thermal and Power Specifications The following notes apply only to Table 5-2 and Table 5-3. Note Definition 1 The TDP and Configurable TDP values are the average power dissipation in junction temperature operating condition limit, for the SKU Segment and Configuration, for which the processor is validated during manufacturing when executing an associated Intel-specified high-complexity workload at the processor IA core frequency corresponding to the configuration and SKU.
Thermal Management 5.2.1 S-Processor Line Thermal and Power Specifications Table 5-2. TDP Specifications (S-Processor Line) Segment and Package Processor IA Cores, Graphics Configuration and TDP Quad Core GT2 91W Quad Core GT2 65W Quad Core GT2 35W Dual Core GT2 51W SProcessor Line LGA Dual Core GT2 35W Dual Core GT1 51W Dual Core GT1 54W Dual Core GT1 35W Processor IA Core Frequency Graphics core Frequency Thermal Design Power (TDP) [w] Base 3.8 GHz to 4.2 GHz 1.
Thermal Management Table 5-3. Package Turbo Specifications (S-Processor Line) (Sheet 2 of 2) Processor IA Cores, Graphics Configuration and TDP Table 5-4. Parameter Min. Hardware Default Max Units Notes Quad Core GT2 65W Power Limit 1 Time (PL1 Tau) Power Limit 1 (PL1) Power Limit 2 (PL2) 0.1 N/A N/A 1 65 1.25*TDP 8 N/A N/A s W W 3,4,5,6 ,7,8,14 Quad Core GT2 35W Power Limit 1 Time (PL1 Tau) Power Limit 1 (PL1) Power Limit 2 (PL2) 0.1 N/A N/A 1 35 1.
Thermal Management Table 5-4. Low Power and TTV Specifications (S-Processor Line) (Sheet 2 of 2) Processor IA Cores, Graphics Configuration and TDP PCG7 Max Power Package C7 (W) 1,4,5 Max Power Package C8 (W) 1,4,5 TTV TDP (W) Min TCASE (°C) 6,7 Max TTV TCASE (°C) Notes: 1. The package C-state power is the worst case power in the system configured as follows: a. Memory configured for DDR3 1333 and populated with two DIMMs per channel. b. DMI and PCIe links are at L1 2.
Thermal Management 5.2.1.1 Thermal Profile for PCG 2015D Processor Figure 5-2. Thermal Test Vehicle Thermal Profile for PCG 2015D Processor Notes: 1. Refer to Table 5-6 for discrete points that constitute the thermal profile. Table 5-6. Thermal Test Vehicle Thermal Profile for PCG 2015D Processor (Sheet 1 of 2) Power (W) TCASE_MAX (C) Power (W) TCASE_MAX (C) 0 43.7 46 53.8 2 44.1 48 54.3 4 44.6 50 54.7 6 45.0 52 55.1 8 45.6 54 55.6 10 45.9 56 56.0 12 46.3 58 56.
Thermal Management Table 5-6. Thermal Test Vehicle Thermal Profile for PCG 2015D Processor (Sheet 2 of 2) Power (W) TCASE_MAX (C) Power (W) TCASE_MAX (C) 38 52.1 84 62.2 40 52.5 86 62.6 42 52.9 88 63.1 44 53.4 90 63.5 46 53.8 92 63.9 5.2.1.2 Thermal Profile for PCG 2015C Processor Figure 5-3. Thermal Test Vehicle Thermal Profile for PCG 2015C Processor Notes: 1. Refer to Table 5-7 for discrete points that constitute the thermal profile. Table 5-7.
Thermal Management Table 5-7. Thermal Test Vehicle Thermal Profile for PCG 2015C Processor (Sheet 2 of 2) Power (W) TCASE_MAX (C) Power (W) TCASE_MAX (C) 18 50.9 52 64.8 20 51.7 53 65.2 22 52.5 54 65.6 24 53.3 56 66.5 26 54.2 58 67.3 28 55.0 60 68.1 30 55.8 62 68.9 32 56.6 64 69.7 34 57.4 65 70.2 5.2.1.3 Thermal Profile for PCG 2015B Processor Figure 5-4. Thermal Test Vehicle Thermal Profile for PCG 2015B Processor Notes: 1.
Thermal Management Table 5-8. Thermal Test Vehicle Thermal Profile for PCG 2015B Processor (Sheet 2 of 2) Power (W) TCASE_MAX (C) Power (W) TCASE_MAX (C) 10 53.3 30 63.5 12 54.3 32 64.5 14 55.3 34 65.5 16 56.4 35 66.1 18 57.4 5.2.1.4 Thermal Profile for PCG 2015A Processor Figure 5-5. Thermal Test Vehicle Thermal Profile for PCG 2015A Processor Notes: 1. Refer to Table 5-9 for discrete points that constitute the thermal profile. Table 5-9.
Thermal Management Table 5-9. 5.2.1.5 Thermal Test Vehicle Thermal Profile for PCG 2015A Processor (Sheet 2 of 2) Power (W) TCASE_MAX (C) Power (W) TCASE_MAX (C) 18 50.9 52 64.8 20 51.7 54 65.6 22 52.5 56 66.5 24 53.3 58 67.3 26 54.2 60 68.1 28 55.0 62 68.9 30 55.8 64 69.7 32 56.6 65 70.2 Thermal Metrology The maximum TTV case temperatures (TCASE-MAX) can be derived from the data in the appropriate TTV thermal profile earlier in this chapter.
Thermal Management The DTS 1.1 implementation consists of two points: a ΨCA at TCONTROL and a ΨCA at DTS = -1. The ΨCA point at DTS = -1 defines the minimum ΨCA required at TDP considering the worst case system design TAMBIENT design point: ΨCA = (TCASE-MAX – TAMBIENT-TARGET) / TDP For example, for a 91 W TDP part, the TCASE maximum is 63.7 °C and at a worst case design point of 40 °C local ambient this will result in: ΨCA = (63.7 – 40) / 91 = 0.
Thermal Management Table 5-10. Digital Thermal Sensor (DTS) 1.1 Thermal Solution Performance Above TCONTROL Processor ΨCA at DTS = TCONTROL1, 2 At System TAMBIENT_MAX = 30 °C ΨCA at DTS = -1 At System TAMBIENT_MAX = 40 °C ΨCA at DTS = -1 At System TAMBIENT_MAX = 45 °C ΨCA at DTS = -1 At System TAMBIENT_MAX = 50 °C 91W 0.45 0.26 0.21 0.15 Quad Core GT2 65W 0.73 0.46 0.39 0.31 35W 1.57 0.74 0.60 0.46 Dual Core GT2 51W 0.83 0.48 0.38 0.28 35W 1.32 0.74 0.60 0.
Thermal Management Figure 5-8. Digital Thermal Sensor (DTS) 1.1 Definition Points Table 5-11. Thermal Margin Slope PCG 2015D 2015C 2015B Die Configuration (Cores/GT) TDP [W] TCC Activation [°C] Temperature Control Offset Thermal Margin Slope [°C/W] Quad Core GT2 91 100 20 0.62 Quad Core GT2 65 100 20 0.85 Dual Core GT2 51 100 20 1.11 Quad Core GT1 65 98 20 0.81 Dual Core GT1 54 100 20 1.04 Quad Core GT2 35 80 16 0.90 Dual Core GT2 35 92 16 1.
Signal Description 6 Signal Description This chapter describes the processor signals. They are arranged in functional groups according to their associated interface or category. The notations in the following table are used to describe the signal type. The signal description also includes the type of buffer used for the particular signal (see the following table). Table 6-1.
Signal Description Table 6-2. DDR3L/-RS Memory Interface (Sheet 2 of 2) Signal Name DDR0_CKE DDR1_CKE DDR0_CS# DDR1_CS# Description Clock Enable: (1 per rank). These signals are used to: • Initialize the SDRAMs during power-up. • Power-down SDRAM ranks. • Place all SDRAM ranks into and out of selfrefresh during STR (Suspend to RAM). Chip Select: (1 per rank). These signals are used to select particular SDRAM components during the active state. There is one Chip Select for each SDRAM rank. Dir.
Signal Description Table 6-3. DDR4 Memory Interface (Sheet 1 of 2) Signal Name Description Dir. Buffer Type Link Type Availability DDR0_DQ[63:0] DDR1_DQ[63:0] Data Buses: Data signals interface to the SDRAM data buses. I/O DDR4 SE All Processor Lines DDR0_DQSP[7:0] DDR0_DQSN[7:0] DDR1_DQSP[7:0] DDR1_DQSN[7:0] Data Strobes: Differential data strobe pairs. The data is captured at the crossing point of DQS during read and write transactions.
Signal Description Table 6-3. DDR4 Memory Interface (Sheet 2 of 2) Signal Name Description Bank Group: BG[0:1] define to which bank group an Active, Read, Write or Precharge command is being applied. BG0 also determines which mode register is to be accessed during a MRS cycle. DDR0_BG[1:0] DDR1_BG[1:0] Dir. Buffer Type Link Type Availability O DDR4 SE All processor lines SO-DIMM, x8 DRAMs, x16 DDP DRAMs devices use BG[1:0].
Signal Description 6.4 Reset and Miscellaneous Signals Table 6-7. Reset and Miscellaneous Signals Signal Name Description Configuration Signals: The CFG signals have a default value of '1' if not terminated on the board. Intel recommends placing test points on the board for CFG pins. • CFG[0]: Stall reset sequence after PCU PLL lock until de-asserted: — 1 = (Default) Normal Operation; No stall. — 0 = Stall. • CFG[1]: Reserved configuration lane.
Signal Description Table 6-8. embedded DisplayPort* Signals (Sheet 2 of 2) Signal Name Description eDP_DISP_UTIL embedded DisplayPort Utility: Output control signal used for brightness correction of embedded LCD displays with backlight modulation. This pin will co-exist with functionality similar to existing BKLTCTL pin on PCH eDP_RCOMP DDI IO Compensation resistor, supporting DP*, eDP* and HDMI* channels. Dir.
Signal Description 6.8 Testability Signals Table 6-11. Testability Signals Description Dir. Buffer Type Link Type BPM#[3:0] Breakpoint and Performance Monitor Signals: Outputs from the processor that indicate the status of breakpoints and programmable counters used for monitoring processor performance. I/O GTL SE All Processor Lines PROC_PRDY# Probe Mode Ready: PROC_PRDY# is a processor output used by debug tools to determine processor debug readiness.
Signal Description Table 6-12. Error and Thermal Protection Signals (Sheet 2 of 2) Signal Name THERMTRIP# 6.10 Description Dir. Buffer Type Link Type Thermal Trip: The processor protects itself from catastrophic overheating by use of an internal thermal sensor. This sensor is set well above the normal operating temperature to ensure that there are no false trips. The processor will stop all executions when the junction temperature exceeds approximately 130 °C.
Signal Description 6.11 Processor Power Rails Table 6-14. Processor Power Rails Signals Signal Name Description Dir. Buffer Type Link Type Availability Vcc Processor IA cores power rail I Power — All Processor Lines VccGT Processor Graphics power rail I Power — All Processor Lines VDDQ System Memory power rail I Power — All Processor Lines VccSA Processor System Agent power rail I Power — All Processor Lines VccIO Processor I/O power rail. Consists of VCCIO and VccIO_DDR.
Signal Description 6.
Electrical Specifications 7 Electrical Specifications 7.1 Processor Power Rails Table 7-1.
Electrical Specifications 7.2 DC Specifications The processor DC specifications in this section are defined at the processor signal pins, unless noted otherwise. • The DC specifications for the DDR3L/-RS/DDR4 signals are listed in the Voltage and Current Specifications section. • The Voltage and Current Specifications section lists the DC specifications for the processor and are valid only while meeting specifications for junction temperature, clock frequency, and input voltages.
Electrical Specifications Table 7-2.
Electrical Specifications 7.2.1.2 VccGT DC Specifications Table 7-3. Processor Graphics (VccGT ) Supply DC Voltage and Current Specifications (Sheet 1 of 2) Symbol Operating voltage IccMAX_GT (SProcessors) Min Typ Max Unit Note1 0.55 — 1.
Electrical Specifications Table 7-3. Symbol Processor Graphics (VccGT ) Supply DC Voltage and Current Specifications (Sheet 2 of 2) Parameter Segment Min Typ Max Unit Note1 Notes: 1. Unless otherwise noted, all specifications in this table are based on estimates and simulations or empirical data. These specifications will be updated with characterized data from silicon measurements at a later date. 2.
Electrical Specifications 7.2.1.4 VccSA DC Specifications Table 7-5. System Agent (VccSA) Supply DC Voltage and Current Specifications Symbol Parameter Segment Min Typ Max — 1.05 — VccSA Voltage for the System Agent S-Processor Line (fixed voltage) TOBVCCSA VccSA Tolerance S-Processor Line ICCMAX_VC Max Current for VCCSA Rail -S-Processor Lines — — 11.
Electrical Specifications 7.2.1.6 VccST DC Specifications Table 7-7. Vcc Sustain (VccST) Supply DC Voltage and Current Specifications Symbol Parameter Segment VccST Processor Vcc Sustain supply voltage All TOBST VccST Tolerance All IccMAX_ST Max Current for VccST S-Processor Lines Min Typ Max Units Notes 1,2 — 1.0 — V 3 mV 3 AC+DC:± 50 — — 60 mA Notes: 1. Unless otherwise noted, all specifications in this table are based on estimates and simulations or empirical data.
Electrical Specifications 7.2.2 Processor Interfaces DC Specifications 7.2.2.1 DDR3L/-RS DC Specifications Table 7-10. DDR3L/-RS Signal Group DC Specifications S-Processor Line Symbol Units Notes1 0.43* VDDQ V 2, 4, 8, 9 — V 3, 4, 8, 9 Parameter VIL Input Low Voltage VIH Input High Voltage Min Typ Max — — 0.
Electrical Specifications 7.2.2.2 DDR4 DC Specifications Table 7-11. DDR4 Signal Group DC Specifications S-Processor Line Symbol VIL VIH Units Notes1 VREF(INT) 0.07*VDDQ V 2, 4, 8, 9, 13 — V 3, 4, 8, 9, 13 Parameter Input Low Voltage Input High Voltage Min Typ Max — — VREF(INT) + 0.
Electrical Specifications 7.2.2.3 PCI Express* Graphics (PEG) DC Specifications Table 7-12. PCI Express* Graphics (PEG) Group DC Specifications Symbol Parameter Min Typ Max Units Notes1 ZTX-DIFF-DC DC Differential Tx Impedance 80 100 120 1, 5 ZRX-DC DC Common Mode Rx Impedance 40 50 60 1, 4 ZRX-DIFF-DC DC Differential Rx Impedance PEG_RCOMP resistance compensation 80 — 120 1 24.75 25 25.25 2, 3 Notes: 1.
Electrical Specifications 7.2.2.6 CMOS DC Specifications Table 7-15. CMOS Signal Group DC Specifications Symbol Parameter Min Max Units Notes1 VIL Input Low Voltage — Vcc * 0.3 V 2, 5 VIH Input High Voltage Vcc * 0.7 — V 2, 4, 5 VOL Output Low Voltage — Vcc * 0.1 V 2 VOH Output High Voltage Vcc * 0.9 — V 2, 4 RON Buffer on Resistance 23 73 - ILI Input Leakage Current — ±150 A 3 Notes: 1.
Electrical Specifications VccST nominal levels will vary between processor families. All PECI devices will operate at the VccST level determined by the processor installed in the system. Table 7-17. PECI DC Electrical Limits Symbol Definition and Conditions Rup Internal pull up resistance VIN Input Voltage Range VHysteresis Hysteresis VIL Input Voltage Low- Edge Threshold Voltage VIH Input Voltage High-Edge Threshold Voltage Cbus Min Max Units Notes1 15 45 3 -0.15 VccST + 0.
Package Mechanical Specifications 8 Package Mechanical Specifications 8.1 Package Mechanical Attributes The -Processor Line use a Flip Chip technology available in a Ball Grid Array (BGA) package. The S-Processor Line uses a Flip Chip technology available in Land Grid Array (LGA). The following table provides an overview of the mechanical attributes of the package. Table 8-1.
Package Mechanical Specifications Table 8-2. Package Storage Specifications (Sheet 2 of 2) Parameter Description RHSUSTAINED STORAGE The maximum device storage relative humidity for the sustained period of time as specified below in Intel Original sealed moisture barrier bag. TIMESUSTAINED STORAGE A prolonged or extended period of time: associated with customer shelf life in Intel Original sealed moisture barrier bag. Min Max 60% @ 24 °C 0 months 6 months Notes 1, 2, 3 1, 2, 3 Notes: 1.
