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Errata
Specification Update 37
KBL042 Last Level Cache Performance Monitoring Events May be Inaccurate
Problem
The performance monitoring events LONGEST_LAT_CACHE.REFERENCE (Event 2EH;
Umask 4FH) and LONGEST_LAT_CACHE.MISS (Event 2EH; Umask 41H) count
requests that reference or miss in the last level cache. However, due to this erratum,
the count may be incorrect.
Implication LONGEST_LAT_CACHE events may be incorrect.
Workaround
None identified. Software may use the following OFFCORE_REQUESTS model-specific
sub events that provide related performance monitoring data:
DEMAND_DATA_RD, DEMAND_CODE_RD, DEMAND_RFO, ALL_DATA_RD,
L3_MISS_DEMAND_DATA_RD, ALL_REQUESTS.
Status For the steppings affected, see the Summary Table of Changes.
KBL043
#GP Occurs Rather Than #DB on Code Page Split Inside an Intel® SGX
Enclave
Problem
When executing within an Intel® SGX (Software Guard Extensions) enclave, a #GP
(general-protection exception) may be delivered instead of a #DB (debug exception)
when an instruction breakpoint is detected. This occurs when the instruction to be
executed spans two pages, the second of which has an entry in the EPCM (enclave
page cache map) that is not valid.
Implication Debugging software may not be invoked when an instruction breakpoint is detected.
Workaround
Software should ensure that all pages containing enclave instructions have valid
EPCM entries.
Status For the steppings affected, see the Summary Table of Changes.
KBL044
Execution of VAESENCLAST Instruction May Produce a #NM Exception
Instead of a #UD Exception
Problem
Execution of VAESENCLAST with VEX.L= 1 should signal a #UD (Invalid Opcode)
exception, however, due to the erratum, a #NM (Device Not Available) exception
may be signaled.
Implication
As a result of this erratum, an operating system may restore AVX and other state
unnecessarily.
Workaround None identified.
Status For the steppings affected, see the Summary Table of Changes.