Other Content

Errata
Specification Update 35
KBL036 Intel® PT OVF Packet May be Lost if Immediately Preceding a TraceStop
Problem
If an Intel PT (Intel® Processor Trace) internal buffer overflow occurs immediately
before software executes a taken branch or event that enters an Intel PT TraceStop
region, the OVF (Overflow) packet may be lost.
Implication
The trace decoder will not see the OVF packet, nor any subsequent packets (e.g.,
TraceStop) that were lost due to overflow.
Workaround None identified.
Status For the steppings affected, see the Summary Table of Changes.
KBL037 WRMSR to IA32_BIOS_UPDT_TRIG May be Counted as Multiple Instructions
Problem
When software loads a microcode update by writing to MSR IA32_BIOS_UPDT_TRIG
(79H) on multiple logical processors in parallel, a logical processor may, due to this
erratum, count the WRMSR instruction as multiple instruction-retired events.
Implication
Performance monitoring with the instruction-retired event may over count by up to
four extra events per instance of WRMSR which targets the IA32_BIOS_UPDT_TRIG
register.
Workaround None identified.
Status For the steppings affected, see the Summary Table of Changes.
KBL038 Branch Instructions May Initialize MPX Bound Registers Incorrectly
Problem
Depending on the current Intel® MPX (Memory Protection Extensions) configuration,
execution of certain branch instructions (near CALL, near RET, near JMP, and Jcc
instructions) without a BND prefix (F2H) initialize the MPX bound registers. Due to
this erratum, execution of such a branch instruction on a user-mode page may not
use the MPX configuration register appropriate to the current privilege level
(BNDCFGU for CPL 3 or BNDCFGS otherwise) for determining whether to initialize the
bound registers; it may thus initialize the bound registers when it should not, or fail
to initialize them when it should.
Implication
After a branch instruction on a user-mode page has executed, a #BR (bound-range)
exception may occur when it should not have or a #BR may not occur when one
should have.
Workaround
If supervisor software is not expected to execute instructions on user-mode pages,
software can avoid this erratum by setting CR4.SMEP[bit 20] to enable supervisor-
mode execution prevention (SMEP). If SMEP is not available or if supervisor software
is expected to execute instructions on user-mode pages, no workaround is identified.
Status For the steppings affected, see the Summary Table of Changes.