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Errata
30 Specification Update
KBL018 PEBS Eventing IP Field May be Incorrect After Not-Taken Branch
Problem
When a PEBS (Precise-Event-Based-Sampling) record is logged immediately after a
not-taken conditional branch (Jcc instruction), the Eventing IP field should contain
the address of the first byte of the Jcc instruction. Due to this erratum, it may instead
contain the address of the instruction preceding the Jcc instruction.
Implication
Performance monitoring software using PEBS may incorrectly attribute PEBS events
that occur on a Jcc to the preceding instruction.
Workaround None identified.
Status For the steppings affected, see the Summary Table of Changes.
KBL019
Debug Exceptions May Be Lost or Misreported Following WRMSR to
IA32_BIOS_UPDT_TRIG
Problem
If the WRMSR instruction writes to the IA32_BIOS_UPDT_TRIG MSR (79H)
immediately after an execution of MOV SS or POP SS that generated a debug
exception, the processor may fail to deliver the debug exception or, if it does, the
DR6 register contents may not correctly reflect the causes of the debug exception.
Implication
Debugging software may fail to operate properly if a debug exception is lost or does
not report complete information.
Workaround
Software should avoid using WRMSR instruction immediately after executing MOV SS
or POP SS
Status For the steppings affected, see the Summary Table of Changes.
KBL020
Complex Interactions With Internal Graphics May Impact Processor
Responsiveness
Problem
Under complex conditions associated with the use of internal graphics, the processor
may exceed the MAX_LAT CSR values (PCI configuration space, offset 03FH,
bits[7:0]).
Implication
When this erratum occurs, the processor responsiveness is affected. Intel has not
observed this erratum with any commercially available software.
Workaround None identified.
Status For the steppings affected, see the Summary Table of Changes.
KBL021 Intel® Processor Trace PSB+ Packets May Contain Unexpected Packets
Problem
Some Intel Processor Trace packets should be issued only between TIP.PGE (Target
IP Packet.Packet Generation Enable) and TIP.PGD (Target IP Packet.Packet
Generation Disable) packets. Due to this erratum, when a TIP.PGE packet is
generated it may be preceded by a PSB+ (Packet Stream Boundary) that incorrectly
includes FUP (Flow Update Packet) and MODE.Exec packets.
Implication Due to this erratum, FUP and MODE.Exec may be generated unexpectedly.
Workaround
Decoders should ignore FUP and MODE.Exec packets that are not between TIP.PGE
and TIP.PGD packets.
Status For the steppings affected, see the Summary Table of Changes.