7th Generation Intel® Processor Family and 8th Generation Intel® Processor Family for U Quad Core Platforms Specification Update Supporting 7th Generation Intel® Core™ Processor Families based on Y/U/H/S-Processor Line, Y/U With iHDCP2.2Processor Line , Intel® Pentium® Processors , Intel® Celeron® Processor and Intel® Xeon® E3-1200 v6 Processors.
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Contents Revision History .................................................................................................................. 4 Preface .............................................................................................................................. 6 Identification Information ..................................................................................................... 8 Summary Tables of Changes ...........................................................................
Revision History Revision History Revision 001 Description Initial release Date August 2016 • Errata 002 Added errata KBL068-078 Updated erratum KBL062 November 2016 Fixed erratum KBL063 • Added SKUs Y/U w/iHDCP2.2, S/H-Processor lines • Added Table 2, S/H-Processor Lines Component Identification • Identification Information Added Table 4, Y-Processor Line With iHDCP2.2 Added Table 6, U-Processor Line With iHDCP2.
Revision History Revision Description Date • Identification Information Updated Table 6, U With iHDCP2.2 Processor Line 008 July 2017 Updated Table 7, S-Processor Line • Errata Added errata KBL102 • Added support for 8th Generation Intel® Core™ Processor Family for U Quad Core Platforms • Errata 009 Added errata KBL103 August 2017 • Identification Information Updated Table 4, “Y With iHDCP2.
Preface Preface This document is an update to the specifications contained in the documents listed in the following Affected Documents/Related Documents table. It is a compilation of device and document errata and specification clarifications and changes, and is intended for hardware system manufacturers and for software developers of applications, operating system, and tools.
Preface Document Title Document Number/Location Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1: Basic Architecture Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A: Instruction Set Reference Manual A-M http://www.intel.com /products/processor/ manuals/index.
Identification Information Identification Information Component Identification via Programming Interface The processor stepping can be identified by the following register contents: Table 1. Y/U/U-Quad Core-Processor Lines Component Identification Reserved Extended Family Extended Model Reserved Processor Type Family Code Model Number Stepping ID 31:28 27:20 19:16 15:14 13:12 11:8 7:4 3:0 0000000b 1000b 00b 0110b 1110b xxxxb Table 2.
Identification Information Component Marking Information Figure 1. Y-Processor Line BGA Top-Side Markings Pin Count: 1515 Package Size: 20 mm x 16.
Identification Information Table 3. Y -Processor Line Processor S-Spec # Processor Step- Number ping Cache Size Func- Processor Processor Graphics LPDDR3 tional Graphics Graphics Maximum Mem. Core Cores Freq. Dynamic (MT/s) Core Freq. Turbo 1 Thermal Slot / Core Freq. Design Socket Rate Power Type Freq. R2ZT I7-7Y75 H-0 4 MB 2 2 0.3 GHz 1.05 GHz 1866 1.3 GHz 3.6 GHz 4.5 W BGA1515 R2ZX I5-7Y54 H-0 4 MB 2 2 0.3 GHz 0.95 GHz 1866 1.2 GHz 3.2 GHz 4.
Identification Information Figure 2. U/U-Quad Core Processor Line BGA Top-Side Markings Pin Count: 1356 Package Size: 42 mm x 24 mm Production (SSPEC): GRP1LINE1: GRP2LINE1 (G2L1): GRP3LINE1 (G3L1): FPOxxxxxSSPEC {eX} Intel logo Table 5. U Processor Line S-Spec Processor Step- Cache Func- Processor Processor Processor Graphics DDR3L LPDDR3 DDR4 Turbo 1 Thermal Slot / # Number ping Size tional Graphics Graphics Maximum Dynamic Mem. Mem. Mem. Core Freq.
Identification Information Table 6. U With iHDCP2.2 Processor Line Core Freq. S-Spec Processor Step- Cache Func- Processor Processor Processor Graphics DDR3L LPDDR3 DDR4 Turbo 1 Thermal Slot / # Number ping Size tional Graphics Graphics Maximum Dynamic Mem. Mem. Mem. Core Freq. Design Socket Core Cores Freq. Freq. (MT/s) (MT/s) (MT/s) Rate Power Type R33Z I7-7600U H-0 4 MB 2 2 0.3 GHz 1.15 GHz 1600 1866 2133 2.8 GHz 3.
Identification Information Table 7. U Quad Core Processor Line S-Spec Processor Step- Cache Func- Processor Processor Processor Graphics DDR3L LPDDR3 DDR4 Turbo 1 Thermal Slot / # Number ping Size tional Graphics Graphics Maximum Dynamic Mem. Mem. Mem. Core Freq. Design Socket Core Cores Freq. Freq. (MT/s) (MT/s) (MT/s) Rate Power Type Core Freq. R3LA I5-8250U Y-0 6 MB 4 2 0.3 GHz 1.1 GHz 1600 1866 2400 1.6 GHz 3.
Identification Information Figure 3. S-Processor Line LGA Top-Side Markings Pin Count: 1151 Package Size: 37.5 mm x 37.
Identification Information Table 8. S-Processor Line Processor S-Spec # Processor Step- Number ping Cache Size Func- Processor Processor Graphics DDR4 DDR3L tional Graphics Graphics Maximum Mem. Mem. Core Cores Freq. Dynamic (MT/s) (MT/s) Turbo 1 Core Freq. Core Freq. Rate Freq. Thermal Slot / Design Socket Power Type R32V I5-7600K B-0 6 MB 4 2 0.35 GHz 1.15 GHz 2400 1600 3.8 GHz 4.2 GHz 91 W LGA1151 R32W I5-7400 B-0 6 MB 4 2 0.
Identification Information Figure 4. H-Processor Line BGA Top-Side Markings Pin Count: 1440 Package Size: 42 mm x 28 mm Production (SSPEC): GRP1LINE1 (G1L1): GRP2LINE1: GRP3LINE1 (G3L1): {eX} FPOxxxxxSSPEC Intel logo Table 9. H-Processor Line Processor S-Spec # Processor Step- Cache Number ping Size Func Processor Processor Graphics DDR4 LPDDR3 tional Graphics Graphics Maximum Mem. Mem. Core Cores Freq. Dynamic (MT/s) (MT/s) Turbo 1 Core Freq. Core Freq. Rate Freq.
Identification Information Figure 5. X-Processor Line LGA Top-Side Markings Pin Count: 2066 Package Size: 45 mm x 52.5 mm Production (SSPEC): GRP1LINE1 (G1L1): {eX} GRP2LINE1: FPOxxxxxSSPEC GRP3LINE1 (G3L1): Intel logo Table 10. X-Processor Line Processor S-Spec # Processor Step- Cache Number ping Size Func Processor Processor Graphics DDR4 LPDDR3 tional Graphics Graphics Maximum Mem. Mem. Core Cores Freq. Dynamic (MT/s) (MT/s) Turbo 1 Core Freq. Core Freq. Rate Freq.
Summary Tables of Changes Summary Tables of Changes The following table indicates the Specification Changes, Errata, Specification Clarifications or Documentation Changes, which apply to the listed processor stepping. Intel intends to fix some of the errata in a future stepping of the component, and to account for the other outstanding issues through documentation or Specification Changes as noted.
Summary Tables of Changes Errata Summary Table Table 11. Errata Summary Table Processor Line / Stepping Y ID U H S X Status Title X No Fix Reported Memory Type May Not Be Used to Access the VMCS and Referenced Data Structures X X No Fix Instruction Fetch May Cause Machine Check if Page Size and Memory Type Was Changed Without Invalidation X X X No Fix Execution of VAESIMC or VAESKEYGENASSIST With An Illegal Value for VEX.
Summary Tables of Changes Processor Line / Stepping Y ID U H S X Status Title H0 H03 H0 H03 J1 23e Y0 42 B0 B0/ S0 B0 KBL018 X X X X X X X X X No Fix PEBS Eventing IP Field May be Incorrect After NotTaken Branch KBL019 X X X X X X X X X No Fix Debug Exceptions May Be Lost or Misreported Following WRMSR to IA32_BIOS_UPDT_TRIG KBL020 X X X X X X X X No Fix Complex Interactions With Internal Graphics May Impact Processor Responsiveness KBL021 X X X X X
Summary Tables of Changes Processor Line / Stepping Y ID U H S X Status Title H0 H03 H0 H03 J1 23e Y0 42 B0 B0/ S0 B0 KBL038 X X X X X X X X X No Fix Branch Instructions May Initialize MPX Bound Registers Incorrectly KBL039 X X X X X X X X X No Fix Writing a Non-Canonical Value to an LBR MSR Does Not Signal a #GP When Intel® PT is Enabled KBL040 X X X X X X X X X No Fix Processor May Run Intel® AVX Code Much Slower Than Expected KBL041 X X X X X X
Summary Tables of Changes Processor Line / Stepping Y ID U H S X H0 H03 H0 H03 J1 23e Y0 42 B0 B0/ S0 B0 KBL059 X X X X X X X X X KBL060 X X X X X X X X KBL061 X X X X X X X X X Title No Fix #GP After RSM May Push Incorrect RFLAGS Value When Intel® PT is Enabled No Fix Access to SGX EPC Page in BLOCKED State is Not KBL062Reported as an SGX-Induced Page Fault No Fix MTF VM Exit on XBEGIN Instruction May Save State Incorrectly Fixed Intel® Turbo Boost Techn
Summary Tables of Changes Processor Line / Stepping Y ID KBL078 U H0 H03 H0 H03 X X X X J1 23e Y0 42 KBL080 KBL081 KBL083 X B0 B0/ S0 B0 X Status No Fix PECI May Not be Functional After Package C10 Resume No Fix Attempts to Retrain a PCIe* Link May be Ignored Fixed PCIe* Expansion ROM Base Address Register May be Incorrect X X X X X X X No Fix PCIe* Port Does Not Support DLL Link Activity Reporting X X X X X X X X No Fix BNDLDX And BNDSTX May Not Signal #GP on
Summary Tables of Changes Processor Line / Stepping Y ID H0 U H03 H0 H03 J1 23e Y0 42 H S X B0 B0/ S0 B0 X X KBL098 Status No Fix Using Different Vendors For 2400 MHz DDR4 UDIMMs May Cause Correctable Errors or a System Hang X X No Fix Two DIMMs Per Channel 2133MHz DDR4 SODIMM Daisy-Chain Systems With Different Vendors May Hang X X No Fix Unpredictable System Behavior May Occur in DDR4 Multi-Rank System No Fix Processor Graphics May Display Incorrectly When EDRAM is Enabled KBL
Errata Errata KBL001 Reported Memory Type May Not Be Used to Access the VMCS and Referenced Data Structures Problem Bits 53:50 of the IA32_VMX_BASIC MSR report the memory type that the processor uses to access the VMCS and data structures referenced by pointers in the VMCS. Due to this erratum, a VMX access to the VMCS or referenced data structures will instead use the memory type that the MTRRs (memory-type range registers) specify for the physical address of the access.
Errata Status For the steppings affected, see the Summary Table of Changes. KBL004 The Corrected Error Count Overflow Bit in IA32_ MC0_STATUS is Not Updated When The UC Bit is Set Problem After a UC (uncorrected) error is logged in the IA32_MC0_STATUS MSR (401H), corrected errors will continue to be counted in the lower 14 bits (bits 51:38) of the Corrected Error Count.
Errata KBL007 x87 FPU Exception (#MF) May be Signaled Earlier Than Expected Problem x87 instructions that trigger #MF normally service interrupts before the #MF. Due to this erratum, if an instruction that triggers #MF is executing when an Enhanced Intel SpeedStep® Technology transitions, an Intel® Turbo Boost Technology transitions, or a Thermal Monitor events occurs, the #MF may be taken before pending interrupts are serviced.
Errata Status For the steppings affected, see the Summary Table of Changes. KBL011 #GP on Segment Selector Descriptor that Straddles Canonical Boundary May Not Provide Correct Exception Error Code Problem During a #GP (General Protection Exception), the processor pushes an error code on to the exception handler’s stack. If the segment selector descriptor straddles the canonical boundary, the error code pushed onto the stack may be incorrect.
Errata KBL014 Intel® PT TIP.PGD May Not Have Target IP Payload Problem When Intel PT (Intel Processor Trace) is enabled and a direct unconditional branch clears IA32_RTIT_STATUS.FilterEn (MSR 571H, bit 0), due to this erratum, the resulting TIP.PGD (Target IP Packet, Packet Generation Disable) may not have an IP payload with the target IP. Implication It may not be possible to tell which instruction in the flow caused the TIP.PGD using only the information in trace packets when this erratum occurs.
Errata KBL018 PEBS Eventing IP Field May be Incorrect After Not-Taken Branch Problem When a PEBS (Precise-Event-Based-Sampling) record is logged immediately after a not-taken conditional branch (Jcc instruction), the Eventing IP field should contain the address of the first byte of the Jcc instruction. Due to this erratum, it may instead contain the address of the instruction preceding the Jcc instruction.
Errata KBL022 Placing an Intel® PT ToPA in Non-WB Memory or Writing It Within a Transactional Region May Lead to System Instability Problem If an Intel PT (Intel® Processor Trace) ToPA (Table of Physical Addresses) is not placed in WB (writeback) memory or is written by software executing within an Intel® TSX (Intel® Transactional Synchronization Extension) transactional region, the system may become unstable. Implication Unusual treatment of the ToPA may lead to system instability.
Errata KBL025 ENCLU[EGETKEY] Ignores KEYREQUEST.MISCMASK Problem The Intel® SGX (Software Guard Extensions) ENCLU[EGETKEY] instruction ignores the MISCMASK field in KEYREQUEST structure when computing a provisioning key, a provisioning seal key, or a seal key. Implication ENCLU[EGETKEY] will return the same key in response to two requests that differ only in the value of KEYREQUEST.MISCMASK. Intel has not observed this erratum with any commercially available software.
Errata KBL029 Transitions Out of 64-bit Mode May Lead to an Incorrect FDP And FIP Problem A transition from 64-bit mode to compatibility or legacy modes may result in cause a subsequent x87 FPU state save to zeroing bits [63:32] of the FDP (x87 FPU Data Pointer Offset) and the FIP (x87 FPU Instruction Pointer Offset). Implication Leaving 64-bit mode may result in incorrect FDP and FIP values when x87 FPU state is saved. Workaround None identified.
Errata KBL033 Processor DDR VREF Signals May Briefly Exceed JEDEC Spec When Entering S3 State Problem Voltage glitch of up to 200mV on the VREF signal lasting for about 1mS may be observed when entering System S3 state. This violates the JEDEC DDR specifications. Implication Intel has not observed this erratum to impact the operation of any commercially available system. Workaround None identified. Status For the steppings affected, see the Summary Table of Changes. KBL034 DR6.
Errata KBL036 Intel® PT OVF Packet May be Lost if Immediately Preceding a TraceStop Problem If an Intel PT (Intel® Processor Trace) internal buffer overflow occurs immediately before software executes a taken branch or event that enters an Intel PT TraceStop region, the OVF (Overflow) packet may be lost. Implication The trace decoder will not see the OVF packet, nor any subsequent packets (e.g., TraceStop) that were lost due to overflow. Workaround None identified.
Errata KBL039 Writing a Non-Canonical Value to an LBR MSR Does Not Signal a #GP When Intel® PT is Enabled If Intel PT (Intel Processor Trace) is enabled, WRMSR will not cause a generalprotection exception (#GP) on an attempt to write a non-canonical value to any of the following MSRs: • MSR_LASTBRANCH_{0 - 31}_FROM_IP (680H – 69FH) • MSR_LASTBRANCH__{0 - 31}_TO_IP (6C0H – 6DFH) Problem • MSR_LASTBRANCH_FROM_IP (1DBH) • MSR_LASTBRANCH_TO_IP (1DCH) • MSR_LASTINT_FROM_IP (1DDH) • MSR_LASTINT_TO_IP (1DEH)In
Errata KBL042 Last Level Cache Performance Monitoring Events May be Inaccurate Problem The performance monitoring events LONGEST_LAT_CACHE.REFERENCE (Event 2EH; Umask 4FH) and LONGEST_LAT_CACHE.MISS (Event 2EH; Umask 41H) count requests that reference or miss in the last level cache. However, due to this erratum, the count may be incorrect. Implication LONGEST_LAT_CACHE events may be incorrect. Workaround None identified.
Errata KBL045 Intel® SGX Enclave Accesses to the APIC-Access Page May Cause APICAccess VM Exits Problem In VMX non-root operation, Intel SGX (Software Guard Extensions) enclave accesses to the APIC-access page may cause APIC-access VM exits instead of page faults. Implication A VMM (virtual-machine monitor) may receive a VM exit due to an access that should have caused a page fault, which would be handled by the guest OS (operating system).
Errata KBL049 Processor Graphics IOMMU Unit May Not Mask DMA Remapping Faults Problem Intel® Virtualization Technology for Directed I/O specification specifies setting the FPD (Fault Processing Disable) field in the context (or extended-context) entry of IOMMU to mask recording of qualified DMA remapping faults for DMA requests processed through that context entry.
Errata KBL052 Integrated Audio Codec May Not be Detected Problem Integrated Audio Codec may lose power when LPSP (Low-Power Single Pipe) mode is enabled for an eDP* (embedded DisplayPort) or DP/HDMI ports. Platforms with Intel® SST (Intel® Smart Sound Technology) enabled are not affected. Implication The Audio Bus driver may attempt to do enumeration of Codecs when eDP or DP/HDMI port enters LPSP mode, due to this erratum, the Integrated Audio Codec will not be detected and audio maybe be lost.
Errata KBL056 CTR_FRZ May Not Freeze Some Counters Problem IA32_PERF_GLOBAL_STATUS.CTR_FRZ (MSR 38EH, bit 59) is set when either (1) IA32_DEBUGCTL.FREEZE_PERFMON_ON_PMI (MSR 1D9H, bit 12) is set and a PMI is triggered, or (2) software sets bit 59 of IA32_PERF_GLOBAL_STATUS_SET (MSR 391H). When set, CTR_FRZ should stop all core performance monitoring counters from counting. However, due to this erratum, IA32_PMC4-7 (MSR C5-C8H) may not stop counting.
Errata KBL059 Instructions Fetch #GP After RSM During Inter® PT May Push Incorrect RFLAGS Value on Stack Problem If Intel PT (Processor Trace) is enabled, a #GP (General Protection Fault) caused by the instruction fetch immediately following execution of an RSM instruction may push an incorrect value for RFLAGS onto the stack. Implication Software that relies on RFLAGS value pushed on the stack under the conditions described may not work properly. Workaround None identified.
Errata KBL063 Performance Monitoring Counters May Undercount When Using CPL Filtering Problem Performance Monitoring counters configured to count only OS or only USR events by setting exactly one of bits 16 or 17 in IA32_PERFEVTSELx MSRs (186H-18DH) may not count for a brief period during the transition to a new CPL. Implication A measurement of ring transitions (using the edge-detect bit 18 in IA32_PERFEVTSELx) may undercount, such as CPL_CYCLES.RING0_TRANS (Event 5CH, Umask 01H).
Errata KBL067 PEBS EventingIP Field May Be Incorrect Under Certain Conditions Problem The EventingIP field in the PEBS (Processor Event-Based Sampling) record reports the address of the instruction that triggered the PEBS event. Under certain complex microarchitectural conditions, the EventingIP field may be incorrect. Implication When this erratum occurs, performance monitoring software may not attribute the PEBS events to the correct instruction. Workaround None identified.
Errata KBL071 HWP’s Maximum_Performance Value is Reset to 0xFF Problem According to HWP (Hardware P-states) specification, the reset value of the Maximum_Performance field (bits [15:8]) in IA32_HWP_REQUEST MSR (774h) should be set to the value of IA32_HWP_CAPABILITIES MSR (771H) Highest_Performance field (bits[7:0]) after reset. Due to this erratum, the reset value of Maximum_Performance is always set to 0xFF. Implication Software may see an unexpected value in Maximum Performance field.
Errata MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS event D2H, umask 01H MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT event D2H, umask 02H MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM event D2H, umask 04H MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE event D2H, umask 08H Implication The listed performance monitoring events may produce incorrect results including PEBS records generated at an incorrect point Workaround None identified Status For the steppings affected, see the Summary Table of Changes.
Errata KBL077 Use of VMASKMOV to Store When Using EPT May Fail Problem Use of VMASKMOV instructions to store data that splits over two pages, when the instruction resides on the first page may cause a hang if EPT (Extended Page Tables) is in use, and the store to the second page requires setting the A/D bits in the EPT entry. Implication Due to this erratum, the CPU may hang on the execution of VMASKMOV Workaround It is possible for the BIOS to contain a workaround for this erratum.
Errata Status For the steppings affected, see the Summary Table of Changes. KBL082 BNDLDX And BNDSTX May Not Signal #GP on Non-Canonical Bound Directory Access Problem BNDLDX and BNDSTX instructions access the bound’s directory and table to load or store bounds. These accesses should signal #GP (general protection exception) when the address is not canonical (i.e. bits 48 to 63 are not the sign extension of bit 47).
Errata KBL086 EDRAM Corrected Error Events May Not be Properly Logged After a Warm Reset Problem After a warm reset, an EDRAM corrected error may not be logged correctly until the associated machine check register is initialized. This erratum may affect IA32_MC8_STATUS or IA32_MC10_STATUS. Implication The EDRAM corrected error information may be lost when this erratum occurs.
Errata KBL090 Violations of Intel® Software Guard Extensions (Intel® SGX) Access-Control Requirements Produce #GP Instead of #PF Problem Intel® Software Guard Extensions (Intel® SGX) define new access-control requirements on memory accesses. A violation of any of these requirements causes a page fault (#PF) that sets bit 15 (SGX) in the page-fault error code. Due to this erratum, these violations instead cause general-protection exceptions (#GP).
Errata KBL093 The Intel PT CR3 Filter is Not Re-evaluated on VM Entry Problem On a VMRESUME or VMLAUNCH with both TraceEn[0] and CR3Filter[7] in IA32_RTIT_CTL (MSR 0570H) set to 1 both before the VM Entry and after, the new value of CR3 is not compared with IA32_RTIT_CR3_MATCH (MSR 0572H).
Errata KBL097 Processor Graphics May Render Incorrectly or May Hang Following Warm Reset With Package C8 Disabled Problem Processor Graphics may not properly restore internal configuration after warm reset when package C8 is disabled. Implication Due to this erratum Processor Graphics may render incorrectly or hang on warm reset. Workaround It is possible for the BIOS to contain a workaround for this erratum. Status For the steppings affected, see the Summary Table of Changes.
Errata KBL101 Processor Graphics May Render Incorrectly When EDRAM is Enabled Problem During high display bandwidth scenarios with EDRAM is enabled, the display engine may generate display artifacts. Implication Due to this erratum, the display engine may generate display artifacts. Workaround It is possible for BIOS to contain processor configuration data and code changes as a workaround for this erratum. Additionally, an updated Intel® Graphics Driver may be needed for this workaround.
Specification Changes Specification Changes There are no Specification Changes in this Specification Update revision.
Specification Clarifications Specification Clarifications There are no specification clarifications in this Specification Update revision.
Documentation Changes Documentation Changes There are no documentation changes in this Specification Update revision.
