User Guide

Errata
Specification Update 47
Implication
Software resuming from system sleep states S3 or S4 and relying on receiving a page
fault from the above enclave accesses may not operate properly.
Workaround
Software can monitor #GP faults to detect that an enclave has been destroyed and
needs to be rebuilt after resuming from S3 or S4
Status For the steppings affected, see the Summary Table of Changes.
KBL091 IA32_RTIT_CR3_MATCH MSR Bits[11:5] Are Treated As Reserved
Problem
Due to this erratum, bits[11:5] in IA32_RTIT_CR3_MATCH (MSR 572H) are reserved;
an MSR write that attempts to set that field to a non-zero value will result in a #GP
fault.
Implication
The inability to write the identified bit field does not affect the functioning of Intel®
PT (Intel® Processor Trace) operation because, as described in erratum SKL061, the
bit field that is the subject of this erratum is not used during Intel PT CR3 filtering.
Workaround
Ensure that bits 11:5 of the value written to IA32_RTIT_CR3_MATCH are zero,
including cases where the selected page-directory-pointer-table base address has
non-zero bits in this range.
Status For the steppings affected, see the Summary Table of Changes.
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