User Guide

Errata
Specification Update 45
KBL082
BNDLDX And BNDSTX May Not Signal #GP on Non-Canonical Bound Directory
Access
Problem
BNDLDX and BNDSTX instructions access the bound’s directory and table to load or
store bounds. These accesses should signal #GP (general protection exception) when
the address is not canonical (i.e. bits 48 to 63 are not the sign extension of bit 47).
Due to this erratum, #GP may not be generated by the processor when a non-
canonical address is used by BNDLDX or BNDSTX for their bound directory memory
access.
Implication Intel has not observed this erratum with any commercially available software.
Workaround Software should use canonical addresses for bound directory accesses.
Status For the steppings affected, see the Summary Table of Changes.
SKL0083 RING_PERF_LIMIT_REASONS May be Incorrect
Problem
Under certain conditions, RING_PERF_LIMIT_REASONS (MSR 6B1H) may incorrectly
assert the OTHER status bit (bit 8) as well as the OTHER log bit (bit 24).
Implication
When this erratum occurs, software using this register will incorrectly report clipping
because of the OTHER reason.
Workaround It is possible for the BIOS to contain a workaround for this erratum.
Status For the steppings affected, see the Summary Table of Changes.
KBL084 Processor May Exceed VCCCore ICCMAX During Multi-core Turbo
Problem
Due to this erratum, the maximum ring frequency limit is incorrectly configured to be
100MHz higher than intended.
Implication
VCCCore ICCMAX may be temporarily exceeded when all the cores are executing at a
Turbo frequency.
Workaround It is possible for the BIOS to contain a workaround for this erratum.
Status For the steppings affected, see the Summary Table of Changes.
KBL085
Performance Monitoring Load Latency Events May Be Inaccurate For Gather
Instructions
Problem
The performance monitoring events MEM_TRANS_RETIRED.LOAD_LATENCY_* (Event
CDH; UMask 01H; any latency) count load instructions whose latency exceed a
predefined threshold, where the loads are randomly selected using the load latency
facility (an extension of PEBS). However due to this erratum, these events may count
incorrectly for VGATHER*/VPGATHER* instructions.
Implication
The Load Latency Performance Monitoring events may be Inaccurate for Gather
instructions.
Workaround None identified
Status For the steppings affected, see the Summary Table of Changes.