User Guide

Errata
Specification Update 43
MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS event D2H, umask 01H
MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT event D2H, umask 02H
MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM event D2H, umask 04H
MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE event D2H, umask 08H
Implication
The listed performance monitoring events may produce incorrect results including
PEBS records generated at an incorrect point
Workaround None identified
Status For the steppings affected, see the Summary Table of Changes.
KBL074 HWP May Generate Thermal Interrupt While Not Enabled
Problem
Due to this erratum, the conditions for HWP (Hardware P-states) to generate a
thermal interrupt on a logical processor may generate thermal interrupts on both
logical processors of that core.
Implication
If two logical processors of a core have different configurations of HWP (e.g. only
enabled on one), an unexpected thermal interrupt may occur on one logical processor
due to the HWP settings of the other logical processor.
Workaround Software should configure HWP consistently on all logical processors of a core.
Status For the steppings affected, see the Summary Table of Changes.
KBL075 Camera Device Does Not Issue an MSI When INTx is Enabled
Problem
When both MSI (Message Signaled Interrupts) and legacy INTx are enabled by the
camera device, INTx is asserted rather than issuing the MSI, in violation of the PCI
Local Bus Specification.
Implication Due to this erratum, camera device interrupts can be lost leading to device failure.
Workaround
The camera device must disable legacy INTx by setting bit 10 of PCICMD (Bus 0;
Device 5; Function 0; Offset 04H) before MSI is enabled
Status For the steppings affected, see the Summary Table of Changes.
KBL076
An x87 Store Instruction Which Pends #PE May Lead to Unexpected
Behavior When EPT A/D is Enabled.
Problem
An x87 store instruction which causes a #PE (Precision Exception) to be pended and
updates an EPT (Extended Page Tables) A/D bit may lead to unexpected behavior.
Implication
The VMM may experience unexpected x87 fault or a machine check exception with
the value of 0x150 in IA32_MC0_STATUS.MCACOD (bits [15:0] in MSR 401H)
Workaround It is possible for the BIOS to contain a workaround for this erratum
Status For the steppings affected, see the Summary Table of Changes.
KBL077 Use of VMASKMOV to Store When Using EPT May Fail
Problem
Use of VMASKMOV instructions to store data that splits over two pages, when the
instruction resides on the first page may cause a hang if EPT (Extended Page Tables)
is in use, and the store to the second page requires setting the A/D bits in the EPT
entry.