User Guide

Errata
42 Specification Update
KBL071 HWP’s Maximum_Performance Value is Reset to 0xFF
Problem
According to HWP (Hardware P-states) specification, the reset value of the
Maximum_Performance field (bits [15:8]) in IA32_HWP_REQUEST MSR (774h) should
be set to the value of IA32_HWP_CAPABILITIES MSR (771H) Highest_Performance
field (bits[7:0]) after reset. Due to this erratum, the reset value of
Maximum_Performance is always set to 0xFF.
Implication
Software may see an unexpected value in Maximum Performance field. Hardware
clipping will prevent invalid performance states.
Workaround None identified.
Status For the steppings affected, see the Summary Table of Changes.
KBL072
HWP’s Guaranteed_Performance and Relevant Status/Interrupt May be
Updated More Than Once Per Second
Problem
According to HWP (Hardware P-states) specification, the Guaranteed_Performance
field (bits[15:8]) in the IA32_HWP_CAPABILITIES MSR (771H) and the
Guaranteed_Performance_Change (bit 0) bit in IA32_HWP_STATUS MSR (777H)
should not be changed more than once per second nor should the thermal interrupt
associated with the change to these fields be signaled more than once per second.
Due to this erratum, the processor may change these fields and generate the
associated interrupt more than once per second
Implication
HWP interrupt rate due to Guaranteed_Performance field change can be higher than
specified
Workaround
Clearing the Guaranteed_Performance_Change status bit no more than once per
second will ensure that interrupts are not generated at too fast a rate
Status For the steppings affected, see the Summary Table of Changes.
KBL073
Some Memory Performance Monitoring Events May Produce Incorrect
Results When Filtering on Either OS or USR Modes
Problem
The memory at-retirement performance monitoring events (listed below) may
produce incorrect results when a performance counter is configured in OS-only or
USR-only modes (bits 17 or 16 in IA32_PERFEVTSELx MSR). Counters with both OS
and USR bits set are not affected by this erratum.
The list of affected memory at-retirement events is as follows:
MEM_INST_RETIRED.STLB_MISS_LOADS event D0H, umask 11H
MEM_INST_RETIRED.STLB_MISS_STORES event D0H, umask 12H
MEM_INST_RETIRED.LOCK_LOADS event D0H, umask 21H
MEM_INST_RETIRED.SPLIT_LOADS event D0H, umask 41H
MEM_INST_RETIRED.SPLIT_STORES event D0H, umask 42H
MEM_LOAD_RETIRED.L2_HIT event D1H, umask 02H
MEM_LOAD_RETIRED.L3_HIT event D1H, umask 04H
MEM_LOAD_RETIRED.L4_HIT event D1H, umask 80H
MEM_LOAD_RETIRED.L1_MISS event D1H, umask 08H
MEM_LOAD_RETIRED.L2_MISS event D1H, umask 10H
MEM_LOAD_RETIRED.L3_MISS event D1H, umask 20H
MEM_LOAD_RETIRED.FB_HIT event D1H, umask 40H