User Guide

Errata
Specification Update 41
KBL067 PEBS EventingIP Field May Be Incorrect Under Certain Conditions
Problem
The EventingIP field in the PEBS (Processor Event-Based Sampling) record reports
the address of the instruction that triggered the PEBS event. Under certain complex
microarchitectural conditions, the EventingIP field may be incorrect.
Implication
When this erratum occurs, performance monitoring software may not attribute the
PEBS events to the correct instruction.
Workaround None identified.
Status For the steppings affected, see the Summary Table of Changes.
KBL068
HWP’s Guaranteed_Performance Updated Only on Configurable TDP
Changes
Problem
According to HWP (Hardware P-states) specification, the Guaranteed_Performance
field (bits[15:8]) in the IA32_HWP_CAPABILITIES MSR (771H) should be updated as
a result of changes in the configuration of TDP, RAPL (Running Average Power Limit),
and other platform tuning options that may have dynamic effects on the actual
guaranteed performance support level. Due to this erratum, the processor will update
the Guaranteed_Performance field only as a result of configurable TDP dynamic
changes.
Implication Software may read a stale value of the Guaranteed _Performance field.
Workaround None identified.
Status For the steppings affected, see the Summary Table of Changes.
KBL069
RF May be Incorrectly Set in The EFLAGS That is Saved on a Fault in PEBS or
BTS
Problem
After a fault due to a failed PEBS (Processor Event Based Sampling) or BTS (Branch
Trace Store) address translation, the RF (resume flag) may be incorrectly set in the
EFLAGS image that is saved.
Implication
When this erratum occurs, a code breakpoint on the instruction following the return
from handling the fault will not be detected. This erratum only happens when the
user does not prevent faults on PEBS or BTS.
Workaround Software should always prevent faults on PEBS or BTS.
Status For the steppings affected, see the Summary Table of Changes.
KBL070 Intel® PT ToPA PMI Does Not Freeze Performance Monitoring Counters
Problem
Due to this erratum, if IA32_DEBUGCTL.FREEZE_PERFMON_ON_PMI (MSR 1D9H, bit
12) is set to 1 when Intel PT (Processor Trace) triggers a ToPA (Table of Physical
Addresses) PMI (PerfMon Interrupt), performance monitoring counters are not frozen
as expected.
Implication
Performance monitoring counters will continue to count for events that occur during
PMI handler execution.
Workaround
PMI handler software can programmatically stop performance monitoring counters
upon entry.
Status For the steppings affected, see the Summary Table of Changes.