User Guide

Errata
Specification Update 39
KBL059
Instructions Fetch #GP After RSM During Inter® PT May Push Incorrect
RFLAGS Value on Stack
Problem
If Intel PT (Processor Trace) is enabled, a #GP (General Protection Fault) caused by
the instruction fetch immediately following execution of an RSM instruction may push
an incorrect value for RFLAGS onto the stack.
Implication
Software that relies on RFLAGS value pushed on the stack under the conditions
described may not work properly.
Workaround None identified.
Status For the steppings affected, see the Summary Table of Changes.
KBL060
Access to SGX EPC Page in BLOCKED State is Not Reported as an SGX-
Induced Page Fault
Problem
If a page fault results from attempting to access a page in the SGX (Intel® Software
Guard Extensions) EPC (Enclave Page Cache) that is in the BLOCKED state, the
processor does not set bit 15 of the error code and thus fails to indicate that the page
fault was SGX-induced.
Implication
Due to this erratum, software may not recognize these page faults as being SGX-
induced.
Workaround
Before using the EBLOCK instruction to marking a page as BLOCKED, software should
use paging to mark the page not present.
Status For the steppings affected, see the Summary Table of Changes.
KBL061 MTF VM Exit on XBEGIN Instruction May Save State Incorrectly
Problem
Execution of an XBEGIN instruction while the monitor trap flag VM-execution control
is 1 will be immediately followed by an MTF VM exit. If advanced debugging of RTM
transactional regions has been enabled, the VM exit will erroneously save as
instruction pointer the address of the XBEGIN instruction instead of the fallback
instruction address specified by the XBEGIN instruction. In addition, it will
erroneously set bit 16 of the pending-debug-exceptions field in the VMCS indicating
that a debug exception or a breakpoint exception occurred.
Implication
Software using the monitor trap flag to debug or trace transactional regions may not
operate properly. Intel has not observed this erratum with any commercially available
software.
Workaround None identified
Status For the steppings affected, see the Summary Table of Changes.
KBL062
Intel® Turbo Boost Technology May be Incorrectly Reported as Supported
on Intel® Core™ i3 U/H/S, Select Intel® Mobile Pentium®, Intel® Mobile
Celeron®, Intel® Pentium® and Intel® Celeron® Processors
Problem
These processors may incorrectly report support for Intel® Turbo Boost Technology
via CPUID.06H.EAX bit 1.
Implication
The CPUID instruction may report Turbo Boost Technology as supported even though
the processor does not permit operation above the Base Frequency.
Workaround None identified.
Status For the steppings affected, see the Summary Table of Changes.