User Guide

Errata
36 Specification Update
Status For the steppings affected, see the Summary Table of Changes.
KBL048 PECI Frequency Limited to 1 MHz
Problem
The PECI (Platform Environmental Control Interface) 3.1 specification’s operating
frequency range is 0.2 MHz to 2 MHz. Due to this erratum, PECI may be unreliable
when operated above 1 MHz.
Implication Platforms attempting to run PECI above 1 MHz may not behave as expected.
Workaround None identified. Platforms should limit PECI operating frequency to 1 MHz.
Status For the steppings affected, see the Summary Table of Changes.
KBL049 Processor Graphics IOMMU Unit May Not Mask DMA Remapping Faults
Problem
Intel® Virtualization Technology for Directed I/O specification specifies setting the
FPD (Fault Processing Disable) field in the context (or extended-context) entry of
IOMMU to mask recording of qualified DMA remapping faults for DMA requests
processed through that context entry. Due to this erratum, the IOMMU unit for
Processor Graphics device may record DMA remapping faults from Processor Graphics
device (Bus: 0; Device: 2; Function: 0) even when the FPD field is set to 1.
Implication
Software may continue to observe DMA remapping faults recorded in the IOMMU
Fault Recording Register even after setting the FPD field.
Workaround
None identified. Software may mask the fault reporting event by setting the IM
(Interrupt Mask) field in the IOMMU Fault Event Control register (Offset 038H in
GFXVTBAR).
Status For the steppings affected, see the Summary Table of Changes.
KBL050 Intel® PT CYCThresh Value of 13 is Not Supported
Problem
Intel PT (Intel® Processor Trace) CYC (Cycle Count) threshold is configured through
CYCThresh field in bits [22:19] of IA32_RTIT_CTL MSR (570H). A value of 13 is
advertised as supported by CPUID (leaf 14H, sub-lead 1H). Due to this erratum, if
CYCThresh is set to 13 then the CYC threshold will be 0 cycles instead of 4096 (213-
1) cycles.
Implication
CYC packets may be issued in higher rate than expected if threshold value of 13 is
used.
Workaround None identified. Software should not use value of 13 for CYC threshold.
Status For the steppings affected, see the Summary Table of Changes.
KBL051 Enabling VMX-Preemption Timer Blocks HDC Operation
Problem
HDC (Hardware Duty Cycling) will not put the physical package into the forced idle
state while any logical processor is in VMX non-root operation and the “activate VMX-
preemption timer” VM-execution control is 1.
Implication
HDC will not provide the desired power reduction when the VMX-preemption timer is
active in VMX non-root operation.
Workaround None identified.
Status For the steppings affected, see the Summary Table of Changes.