User Guide

Errata
34 Specification Update
Workaround It is possible for the BIOS to contain a workaround
Status For the steppings affected, see the Summary Table of Changes.
KBL041 Intel® PT Buffer Overflow May Result in Incorrect Packets
Problem
Under complex micro-architectural conditions, an Intel PT (Processor Trace) OVF
(Overflow) packet may be issued after the first byte of a multi-byte CYC (Cycle
Count) packet, instead of any remaining bytes of the CYC.
Implication
When this erratum occurs, the splicing of the CYC and OVF packets may prevent the
Intel PT decoder from recognizing the overflow. The Intel PT decoder may then
encounter subsequent packets that are not consistent with expected behavior.
Workaround
None Identified. The decoder may be able to recognize that this erratum has
occurred when a two-byte CYC packet is followed by a single byte CYC, where the
latter 2 bytes are 0xf302, and where the CYC packets are followed by a FUP (Flow
Update Packet) and a PSB+ (Packet Stream Boundary+). It should then treat the
two CYC packets as indicating an overflow.
Status For the steppings affected, see the Summary Table of Changes.
KBL042 Last Level Cache Performance Monitoring Events May be Inaccurate
Problem
The performance monitoring events LONGEST_LAT_CACHE.REFERENCE (Event 2EH;
Umask 4FH) and LONGEST_LAT_CACHE.MISS (Event 2EH; Umask 41H) count
requests that reference or miss in the last level cache. However, due to this erratum,
the count may be incorrect.
Implication LONGEST_LAT_CACHE events may be incorrect.
Workaround
None identified. Software may use the following OFFCORE_REQUESTS model-specific
sub events that provide related performance monitoring data:
DEMAND_DATA_RD, DEMAND_CODE_RD, DEMAND_RFO, ALL_DATA_RD,
L3_MISS_DEMAND_DATA_RD, ALL_REQUESTS.
Status For the steppings affected, see the Summary Table of Changes.
KBL043
#GP Occurs Rather Than #DB on Code Page Split Inside an Intel® SGX
Enclave
Problem
When executing within an Intel® SGX (Software Guard Extensions) enclave, a #GP
(general-protection exception) may be delivered instead of a #DB (debug exception)
when an instruction breakpoint is detected. This occurs when the instruction to be
executed spans two pages, the second of which has an entry in the EPCM (enclave
page cache map) that is not valid.
Implication Debugging software may not be invoked when an instruction breakpoint is detected.
Workaround
Software should ensure that all pages containing enclave instructions have valid
EPCM entries.
Status For the steppings affected, see the Summary Table of Changes.