User Guide

Errata
Specification Update 33
Implication
Performance monitoring with the instruction-retired event may over count by up to
four extra events per instance of WRMSR which targets the IA32_BIOS_UPDT_TRIG
register.
Workaround None identified.
Status For the steppings affected, see the Summary Table of Changes.
KBL038 Branch Instructions May Initialize MPX Bound Registers Incorrectly
Problem
Depending on the current Intel® MPX (Memory Protection Extensions) configuration,
execution of certain branch instructions (near CALL, near RET, near JMP, and Jcc
instructions) without a BND prefix (F2H) initialize the MPX bound registers. Due to
this erratum, execution of such a branch instruction on a user-mode page may not
use the MPX configuration register appropriate to the current privilege level
(BNDCFGU for CPL 3 or BNDCFGS otherwise) for determining whether to initialize the
bound registers; it may thus initialize the bound registers when it should not, or fail
to initialize them when it should.
Implication
After a branch instruction on a user-mode page has executed, a #BR (bound-range)
exception may occur when it should not have or a #BR may not occur when one
should have.
Workaround
If supervisor software is not expected to execute instructions on user-mode pages,
software can avoid this erratum by setting CR4.SMEP[bit 20] to enable supervisor-
mode execution prevention (SMEP). If SMEP is not available or if supervisor software
is expected to execute instructions on user-mode pages, no workaround is identified.
Status For the steppings affected, see the Summary Table of Changes.
KBL039
Writing a Non-Canonical Value to an LBR MSR Does Not Signal a #GP When
Intel® PT is Enabled
Problem
If Intel PT (Intel Processor Trace) is enabled, WRMSR will not cause a general-
protection exception (#GP) on an attempt to write a non-canonical value to any of
the following MSRs:
• MSR_LASTBRANCH_{0 - 31}_FROM_IP (680H – 69FH)
• MSR_LASTBRANCH__{0 - 31}_TO_IP (6C0H – 6DFH)
• MSR_LASTBRANCH_FROM_IP (1DBH)
• MSR_LASTBRANCH_TO_IP (1DCH)
• MSR_LASTINT_FROM_IP (1DDH)
• MSR_LASTINT_TO_IP (1DEH)Instead the same behavior will occur as if a canonical
value had been written. Specifically, the WRMSR will be dropped and the MSR value
will not be changed.
Implication Due to this erratum, an expected #GP may not be signaled.
Workaround None identified.
Status For the steppings affected, see the Summary Table of Changes.
KBL040 Processor May Run Intel® AVX Code Much Slower Than Expected
Problem After a C6 state exit, the execution rate of AVX instructions may be reduced.
Implication Applications using AVX instructions may run slower than expected.