User Guide

Errata
Specification Update 31
KBL031 ENCLS[ECREATE] Causes #GP if Enclave Base Address is Not Canonical
Problem
The ENCLS[ECREATE] instruction uses an SECS (SGX enclave control structure)
referenced by the SRCPAGE pointer in the PAGEINFO structure, which is referenced
by the RBX register. Due to this erratum, the instruction causes a #GP (general-
protection fault) if the SECS attributes indicate that the enclave should operate in 64-
bit mode and the enclave base linear address in the SECS is not canonical.
Implication
System software will incur a general-protection fault if it mistakenly programs the
SECS with a non-canonical address. Intel has not observed this erratum with any
commercially available software.
Workaround
System software should always specify a canonical address as the base address of
the 64-bit mode enclave.
Status For the steppings affected, see the Summary Table of Changes.
KBL032 Processor Graphics IOMMU Unit May Report Spurious Faults
Problem
The IOMMU unit for Processor Graphics pre-fetches context (or extended-context)
entries to improve performance. Due to the erratum, the IOMMU unit may report
spurious DMA remapping faults if prefetching encounters a context (or extended-
context) entry which is not marked present.
Implication
Software may observe spurious DMA remapping faults when the present bit for the
context (or extended-context) entry corresponding to the Processor Graphics device
(Bus: 0; Device: 2; Function: 0) is cleared. These faults may be reported when the
Processor Graphics device is quiescent.
Workaround
None identified. Instead of marking a context not present, software should mark the
context (or extended-context) entry present while using the page table to indicate all
the memory pages referenced by the context entry is not present.
Status For the steppings affected, see the Summary Table of Changes.
KBL033
Processor DDR VREF Signals May Briefly Exceed JEDEC Spec When Entering
S3 State
Problem
Voltage glitch of up to 200mV on the VREF signal lasting for about 1mS may be
observed when entering System S3 state. This violates the JEDEC DDR specifications.
Implication
Intel has not observed this erratum to impact the operation of any commercially
available system.
Workaround None identified.
Status For the steppings affected, see the Summary Table of Changes.