User Guide

Errata
30 Specification Update
KBL027
ENCLU[EREPORT] May Cause a #GP When TARGETINFO.MISCSELECT is Non-
Zero
Problem
The Intel® SGX (Software Guard extensions) ENCLU[EREPORT] instruction may
cause a #GP (general protection fault) if any bit is set in TARGETINFO structure’s
MISCSELECT field.
Implication This erratum may cause unexpected general-protection exceptions inside enclaves.
Workaround
When executing the ENCLU[EREPORT] instruction, software should ensure the bits set
in TARGETINFO.MISCSELECT are a subset of the bits set in the current SECS’s
MISCSELECT field.
Status For the steppings affected, see the Summary Table of Changes.
KBL028
A VMX Transition Attempting to Load a Non-Existent MSR May Result in a
Shutdown
Problem
A VMX transition may result in a shutdown (without generating a machine-check
event) if a non-existent MSR is included in the associated MSR-load area. When such
a shutdown occurs, a machine check error will be logged with
IA32_MCi_STATUS.MCACOD (bits [15:0]) of 406H, but the processor does not issue
the special shutdown cycle. A hardware reset must be used to restart the processor.
Implication Due to this erratum, the hypervisor may experience an unexpected shutdown.
Workaround Software should not configure VMX transitions to load non-existent MSRs.
Status For the steppings affected, see the Summary Table of Changes.
KBL029 Transitions Out of 64-bit Mode May Lead to an Incorrect FDP And FIP
Problem
A transition from 64-bit mode to compatibility or legacy modes may result in cause a
subsequent x87 FPU state save to zeroing bits [63:32] of the FDP (x87 FPU Data
Pointer Offset) and the FIP (x87 FPU Instruction Pointer Offset).
Implication
Leaving 64-bit mode may result in incorrect FDP and FIP values when x87 FPU state
is saved.
Workaround
None identified. 64-bit software should save x87 FPU state before leaving 64-bit
mode if it needs to access the FDP and/or FIP values.
Status For the steppings affected, see the Summary Table of Changes.
KBL030 Intel® PT FUP May be Dropped After OVF
Problem
Some Intel PT (Intel Processor Trace) OVF (Overflow) packets may not be followed by
a FUP (Flow Update Packet) or TIP.PGE (Target IP Packet, Packet Generation Enable).
Implication When this erratum occurs, an unexpected packet sequence is generated.
Workaround
When it encounters an OVF without a following FUP or TIP.PGE, the Intel PT trace
decoder should scan for the next TIP, TIP.PGE, or PSB+ to resume operation.
Status For the steppings affected, see the Summary Table of Changes.