User Guide

Errata
Specification Update 29
Status For the steppings affected, see the Summary Table of Changes.
KBL023 VM Entry That Clears TraceEn May Generate a FUP
Problem
If VM entry clears Intel® PT (Intel Processor Trace) IA32_RTIT_CTL.TraceEn (MSR
570H, bit 0) while PacketEn is 1 then a FUP (Flow Update Packet) will precede the
TIP.PGD (Target IP Packet, Packet Generation Disable). VM entry can clear TraceEn if
the VM-entry MSR-load area includes an entry for the IA32_RTIT_CTL MSR.
Implication
When this erratum occurs, an unexpected FUP may be generated that creates the
appearance of an asynchronous event taking place immediately before or during the
VM entry.
Workaround
The Intel PT trace decoder may opt to ignore any FUP whose IP matches that of a VM
entry instruction.
Status For the steppings affected, see the Summary Table of Changes.
KBL024
Performance Monitor Event For Outstanding Offcore Requests And Snoop
Requests May be Incorrect
Problem
The performance monitor event OFFCORE_REQUESTS_OUTSTANDING (Event 60H,
any Umask Value) should count the number of offcore outstanding transactions each
cycle. Due to this erratum, the counts may be higher or lower than expected.
Implication
The performance monitor event OFFCORE_REQUESTS_OUTSTANDING may reflect an
incorrect count.
Workaround None identified.
Status For the steppings affected, see the Summary Table of Changes.
KBL025 ENCLU[EGETKEY] Ignores KEYREQUEST.MISCMASK
Problem
The Intel® SGX (Software Guard Extensions) ENCLU[EGETKEY] instruction ignores
the MISCMASK field in KEYREQUEST structure when computing a provisioning key, a
provisioning seal key, or a seal key.
Implication
ENCLU[EGETKEY] will return the same key in response to two requests that differ
only in the value of KEYREQUEST.MISCMASK. Intel has not observed this erratum
with any commercially available software.
Workaround
When executing the ENCLU[EGETKEY] instruction, software should ensure the bits set
in KEYREQUEST.MISCMASK are a subset of the bits set in the current SECS’s
MISCSELECT field.
Status For the steppings affected, see the Summary Table of Changes.
KBL026 POPCNT Instruction May Take Longer to Execute Than Expected
Problem
POPCNT instruction execution with a 32 or 64 bit operand may be delayed until
previous non-dependent instructions have executed.
Implication
Software using the POPCNT instruction may experience lower performance than
expected.
Workaround None identified
Status For the steppings affected, see the Summary Table of Changes.