User Guide

Errata
Specification Update 27
Status For the steppings affected, see the Summary Table of Changes.
KBL015
Operand-Size Override Prefix Causes 64-bit Operand Form of MOVBE
Instruction to Cause a #UD
Problem
Execution of a 64 bit operand MOVBE instruction with an operand-size override
instruction prefix (66H) may incorrectly cause an invalid-opcode exception (#UD).
Implication
A MOVBE instruction with both REX.W=1 and a 66H prefix will unexpectedly cause an
#UD (invalid-opcode exception). Intel has not observed this erratum with any
commercially available software.
Workaround Do not use a 66H instruction prefix with a 64-bit operand MOVBE instruction.
Status For the steppings affected, see the Summary Table of Changes.
KBL016
Execution of FXSAVE or FXRSTOR With the VEX Prefix May Produce a #NM
Exception
Problem
Attempt to use FXSAVE or FXRSTOR with a VEX prefix should produce a #UD
(Invalid-Opcode) exception. If either the TS or EM flag bits in CR0 are set, a #NM
(device-not-available) exception will be raised instead of #UD exception.
Implication
Due to this erratum a #NM exception may be signaled instead of a #UD exception on
an FXSAVE or an FXRSTOR with a VEX prefix.
Workaround Software should not use FXSAVE or FXRSTOR with the VEX prefix.
Status For the steppings affected, see the Summary Table of Changes.
KBL017
WRMSR May Not Clear The Sticky Count Overflow Bit in The
IA32_MCi_STATUS MSRs’ Corrected Error Count Field
Problem
The sticky count overflow bit is the most significant bit (bit 52) of the Corrected Error
Count Field (bits[52:38]) in IA32_MCi_STATUS MSRs. Once set, the sticky count
overflow bit may not be cleared by a WRMSR instruction. When this occurs, that bit
can only be cleared by power-on reset.
Implication
Software that uses the Corrected Error Count field and expects to be able to clear the
sticky count overflow bit may misinterpret the number of corrected errors when the
sticky count overflow bit is set. This erratum does not affect threshold-based CMCI
(Corrected Machine Check Error Interrupt) signaling.
Workaround None identified.
Status For the steppings affected, see the Summary Table of Changes.
KBL018 PEBS Eventing IP Field May be Incorrect After Not-Taken Branch
Problem
When a PEBS (Precise-Event-Based-Sampling) record is logged immediately after a
not-taken conditional branch (Jcc instruction), the Eventing IP field should contain
the address of the first byte of the Jcc instruction. Due to this erratum, it may instead
contain the address of the instruction preceding the Jcc instruction.
Implication
Performance monitoring software using PEBS may incorrectly attribute PEBS events
that occur on a Jcc to the preceding instruction.
Workaround None identified.