User Guide

Errata
26 Specification Update
Status For the steppings affected, see the Summary Table of Changes.
KBL011
#GP on Segment Selector Descriptor that Straddles Canonical Boundary May
Not Provide Correct Exception Error Code
Problem
During a #GP (General Protection Exception), the processor pushes an error code on
to the exception handler’s stack. If the segment selector descriptor straddles the
canonical boundary, the error code pushed onto the stack may be incorrect.
Implication
An incorrect error code may be pushed onto the stack. Intel has not observed this
erratum with any commercially available software.
Workaround None identified.
Status For the steppings affected, see the Summary Table of Changes.
KBL012 The SMSW Instruction May Execute Within an Enclave
Problem
The SMSW instruction is illegal within an SGX (Software Guard Extensions) enclave,
and an attempt to execute it within an enclave should result in a #UD (invalid-opcode
exception). Due to this erratum, the instruction executes normally within an enclave
and does not cause a #UD.
Implication
The SMSW instruction provides access to CR0 bits 15:0 and will provide that
information inside an enclave. These bits include NE, ET, TS, EM, MP and PE.
Workaround
None identified. If SMSW execution inside an enclave is unacceptable, system
software should not enable SGX.
Status For the steppings affected, see the Summary Table of Changes.
KBL013
WRMSR to IA32_BIOS_UPDT_TRIG Concurrent With an SMX SENTER/SEXIT
May Result in a System Hang
Problem
Performing WRMSR to IA32_BIOS_UPDT_TRIG (MSR 79H) on a logical processor
while another logical processor is executing an SMX (Safer Mode Extensions)
SENTER/SEXIT operation (GETSEC[SENTER] or GETSEC[SEXIT] instruction) may
cause the processor to hang.
Implication
When this erratum occurs, the system will hang. Intel has not observed this erratum
with any commercially available system.
Workaround None identified.
Status For the steppings affected, see the Summary Table of Changes.
KBL014 Intel® PT TIP.PGD May Not Have Target IP Payload
Problem
When Intel PT (Intel Processor Trace) is enabled and a direct unconditional branch
clears IA32_RTIT_STATUS.FilterEn (MSR 571H, bit 0), due to this erratum, the
resulting TIP.PGD (Target IP Packet, Packet Generation Disable) may not have an IP
payload with the target IP.
Implication
It may not be possible to tell which instruction in the flow caused the TIP.PGD using
only the information in trace packets when this erratum occurs.
Workaround
The Intel PT trace decoder can compare direct unconditional branch targets in the
source with the FilterEn address range(s) to determine which branch cleared FilterEn.