User Guide

Errata
Specification Update 25
KBL007 x87 FPU Exception (#MF) May be Signaled Earlier Than Expected
Problem
x87 instructions that trigger #MF normally service interrupts before the #MF. Due to
this erratum, if an instruction that triggers #MF is executing when an Enhanced Intel
SpeedStep® Technology transitions, an Intel® Turbo Boost Technology transitions,
or a Thermal Monitor events occurs, the #MF may be taken before pending interrupts
are serviced.
Implication Software may observe #MF being signaled before pending interrupts are serviced.
Workaround None identified.
Status For the steppings affected, see the Summary Table of Changes.
KBL008 Incorrect FROM_IP Value For an RTM Abort in BTM or BTS May be Observed
Problem
During RTM (Restricted Transactional Memory) operation when branch tracing is
enabled using BTM (Branch Trace Message) or BTS (Branch Trace Store), the
incorrect EIP value (From_IP pointer) may be observed for an RTM abort.
Implication
Due to this erratum, the From_IP pointer may be the same as that of the
immediately preceding taken branch.
Workaround None identified.
Status For the steppings affected, see the Summary Table of Changes.
KBL009
DR6 Register May Contain an Incorrect Value When a MOV to SS or POP SS
Instruction is Followed by an XBEGIN Instruction
Problem
If XBEGIN is executed immediately after an execution of MOV to SS or POP SS, a
transactional abort occurs and the logical processor restarts execution from the
fallback instruction address. If execution of the instruction at that address causes a
debug exception, bits [3:0] of the DR6 register may contain an incorrect value.
Implication
When the instruction at the fallback instruction address causes a debug exception,
DR6 may report a breakpoint that was not triggered by that instruction, or it may fail
to report a breakpoint that was triggered by the instruction.
Workaround
Avoid following a MOV SS or POP SS instruction immediately with an XBEGIN
instruction.
Status For the steppings affected, see the Summary Table of Changes.
KBL010
Opcode Bytes F3 0F BC May Execute As TZCNT Even When TZCNT Not
Enumerated by CPUID
Problem
If CPUID.(EAX=07H, ECX=0):EBX.BMI1 (bit 3) is 1 then opcode bytes F3 0F BC
should be interpreted as TZCNT otherwise they will be interpreted as REP BSF. Due to
this erratum, opcode bytes F3 0F BC may execute as TZCNT even if
CPUID.(EAX=07H, ECX=0):EBX.BMI1 (bit 3) is 0.
Implication
Software that expects REP prefix before a BSF instruction to be ignored may not
operate correctly since there are cases in which BSF and TZCNT differ with regard to
the flags that are set and how the destination operand is established.
Workaround
Software should use the opcode bytes F3 0F BC only if CPUID.(EAX=07H,
ECX=0):EBX.BMI1 (bit 3) is 1 and only if the functionality of TZCNT (and not BSF) is
desired.