User Guide

Errata
24 Specification Update
Status For the steppings affected, see the Summary Table of Changes.
KBL004
The Corrected Error Count Overflow Bit in IA32_ MC0_STATUS is Not
Updated When The UC Bit is Set
Problem
After a UC (uncorrected) error is logged in the IA32_MC0_STATUS MSR (401H),
corrected errors will continue to be counted in the lower 14 bits (bits 51:38) of the
Corrected Error Count. Due to this erratum, the sticky count overflow bit (bit 52) of
the Corrected Error Count will not get updated when the UC bit (bit 61) is set to 1.
Implication
The Corrected Error Count Overflow indication will be lost if the overflow occurs after
an uncorrectable error has been logged.
Workaround None identified
Status For the steppings affected, see the Summary Table of Changes.
KBL005
VM Exit May Set IA32_EFER.NXE When IA32_MISC_ENABLE Bit 34 is Set to
1
Problem
When “XD Bit Disable” in the IA32_MISC_ENABLE MSR (1A0H) bit 34 is set to 1, it
should not be possible to enable the “execute disable” feature by setting
IA32_EFER.NXE. Due to this erratum, a VM exit that occurs with the 1-setting of the
“load IA32_EFER” VM-exit control may set IA32_EFER.NXE even if
IA32_MISC_ENABLE bit 34 is set to 1. This erratum can occur only if
IA32_MISC_ENABLE bit 34 was set by guest software in VMX non-root operation.
Implication
Software in VMX root operation may execute with the “execute disable” feature
enabled despite the fact that the feature should be disabled by the
IA32_MISC_ENABLE MSR. Intel has not observed this erratum with any commercially
available software.
Workaround
A virtual-machine monitor should not allow guest software to write to the
IA32_MISC_ENABLE MSR
Status For the steppings affected, see the Summary Table of Changes.
KBL006
SMRAM State-Save Area Above the 4GB Boundary May Cause Unpredictable
System Behavior
Problem
If BIOS uses the RSM instruction to load the SMBASE register with a value that would
cause any part of the SMRAM state-save area to have an address above 4-GBytes,
subsequent transitions into and out of SMM (system-management mode) might save
and restore processor state from incorrect addresses.
Implication
This erratum may cause unpredictable system behavior. Intel has not observed this
erratum with any commercially available system.
Workaround
Ensure that the SMRAM state-save area is located entirely below the 4GB address
boundary.
Status For the steppings affected, see the Summary Table of Changes.