User Guide

Errata
Specification Update 23
Errata
KBL001
Reported Memory Type May Not Be Used to Access the VMCS and
Referenced Data Structures
Problem
Bits 53:50 of the IA32_VMX_BASIC MSR report the memory type that the processor
uses to access the VMCS and data structures referenced by pointers in the VMCS.
Due to this erratum, a VMX access to the VMCS or referenced data structures will
instead use the memory type that the MTRRs (memory-type range registers) specify
for the physical address of the access.
Implication
Bits 53:50 of the IA32_VMX_BASIC MSR report that the WB (write-back) memory
type will be used but the processor may use a different memory type.
Workaround
Software should ensure that the VMCS and referenced data structures are located at
physical addresses that are mapped to WB memory type by the MTRRs.
Status For the steppings affected, see the Summary Table of Changes.
KBL002
Instruction Fetch May Cause Machine Check if Page Size and Memory Type
Was Changed Without Invalidation
Problem
This erratum may cause a machine-check error
(IA32_MCi_STATUS.MCACOD=0150H) on the fetch of an instruction that crosses a 4-
KByte address boundary. It applies only if (1) the 4-KByte linear region on which the
instruction begins is originally translated using a 4-KByte page with the WB memory
type; (2) the paging structures are later modified so that linear region is translated
using a large page (2-MByte, 4-MByte, or 1-GByte) with the UC memory type; and
(3) the instruction fetch occurs after the paging-structure modification but before
software invalidates any TLB entries for the linear region.
Implication
Due to this erratum an unexpected machine check with error code 0150H may occur,
possibly resulting in a shutdown. Intel has not observed this erratum with any
commercially available software.
Workaround
Software should not write to a paging-structure entry in a way that would change, for
any linear address, both the page size and the memory type. It can instead use the
following algorithm: first clear the P flag in the relevant paging-structure entry (e.g.,
PDE); then invalidate any translations for the affected linear addresses; and then
modify the relevant paging-structure entry to set the P flag and establish the new
page size and memory type.
Status For the steppings affected, see the Summary Table of Changes.
KBL003
Execution of VAESIMC or VAESKEYGENASSIST With An Illegal Value for
VEX.vvvv May Produce a #NM Exception
Problem
The VAESIMC and VAESKEYGENASSIST instructions should produce a #UD (Invalid-
Opcode) exception if the value of the vvvv field in the VEX prefix is not 1111b. Due to
this erratum, if CR0.TS is “1”, the processor may instead produce a #NM (Device-
Not-Available) exception.
Implication
Due to this erratum, some undefined instruction encodings may produce a #NM
instead of a #UD exception.
Workaround
Software should always set the vvvv field of the VEX prefix to 1111b for instances of
the VAESIMC and VAESKEYGENASSIST instructions.