7th Generation Intel® Processor Family Specification Update Supporting 7th Generation Intel® Core™ Processor Families based on Y/U/H/S-Processor Line, Y/U With iHDCP2.
Revision History You may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning Intel products described herein. You agree to grant Intel a non-exclusive, royalty-free license to any patent claim thereafter drafted which includes subject matter disclosed herein. No license (express or implied, by estoppel or otherwise) to any intellectual property rights is granted by this document.
Revision History Contents Revision History .................................................................................................................. 4 Preface .............................................................................................................................. 5 Identification Information ..................................................................................................... 7 Summary Tables of Changes .........................................................
Revision History Revision History Revision 001 Description Date Initial release August 2016 • Errata 002 Added errata KBL068-078 November 2016 Updated erratum KBL062 Fixed erratum KBL063 • Added SKUs Y/U w/iHDCP2.2, S/H-Processor lines • Added Table 2, S/H-Processor Lines Component Identification • Identification Information Added Table 4, Y-Processor Line With iHDCP2.2 Added Table 6, U-Processor Line With iHDCP2.
Preface Preface This document is an update to the specifications contained in the documents listed in the following Affected Documents/Related Documents table. It is a compilation of device and document errata and specification clarifications and changes, and is intended for hardware system manufacturers and for software developers of applications, operating system, and tools.
Preface Nomenclature Errata are design defects or errors. Errata may cause the processor’s behavior to deviate from published specifications. Hardware and software designed to be used with any given stepping must assume that all errata documented for that stepping are present on all devices. Specification Changes are modifications to the current published specifications. These changes will be incorporated in the next release of the specifications.
Identification Information Identification Information Component Identification via Programming Interface The processor stepping can be identified by the following register contents: Table 1. Y/U-Processor Lines Component Identification Reserved Extended Family Extended Model Reserved Processor Type Family Code Model Number Stepping ID 31:28 27:20 19:16 15:14 13:12 11:8 7:4 3:0 0000000b 1000b 00b 0110b 1110b xxxxb Table 2.
Identification Information Component Marking Information Figure 1. Y-Processor Line BGA Top-Side Markings Pin Count: 1515 Package Size: 20 mm x 16.
Identification Information Table 3. Y -Processor Line Processor S-Spec # Processor Step- Number ping Cache Size Func- Processor Processor Graphics LPDDR3 tional Graphics Graphics Maximum Mem. Core Cores Freq. Dynamic (MT/s) Core Freq. Turbo 1 Thermal Slot / Core Freq. Design Socket Rate Power Type Freq. R2ZT I7-7Y75 H-0 4 MB 2 2 0.3 GHz 1.05 GHz 1866 1.3 GHz 3.6 GHz 4.5 W BGA1515 R2ZX I5-7Y54 H-0 4 MB 2 2 0.3 GHz 0.95 GHz 1866 1.2 GHz 3.2 GHz 4.
Identification Information Figure 2. U-Processor Line BGA Top-Side Markings Pin Count: 1356 Package Size: 42 mm x 24 mm Production (SSPEC): GRP1LINE1: GRP2LINE1 (G2L1): GRP3LINE1 (G3L1): FPOxxxxxSSPEC {eX} Intel logo Table 5. U -Processor Line S-Spec Processor Step- Cache Func- Processor Processor Processor Graphics DDR3L LPDDR3 DDR4 Turbo 1 Thermal Slot / # Number ping Size tional Graphics Graphics Maximum Dynamic Mem. Mem. Mem. Core Freq.
Identification Information Table 6. U-Processor Line With iHDCP2.2 S-Spec Processor Step- Cache Func- Processor Processor Processor Graphics DDR3L LPDDR3 DDR4 Turbo 1 Thermal Slot / # Number ping Size tional Graphics Graphics Maximum Dynamic Mem. Mem. Mem. Core Freq. Design Socket Core Cores Freq. Freq. (MT/s) (MT/s) (MT/s) Rate Power Type Core Freq. R33Z I7-7600U H-0 4 MB 2 2 0.3 GHz 1.15 GHz 1600 1866 2133 2.8 GHz 3.
Identification Information Figure 3. S-Processor Line LGA Top-Side Markings Pin Count: 1151 Package Size: 37.5 mm x 37.
Identification Information Table 7. S-Processor Line Processor S-Spec # Processor Step- Number ping Cache Size Func- Processor Processor Graphics DDR4 DDR3L tional Graphics Graphics Maximum Mem. Mem. Core Cores Freq. Dynamic (MT/s) (MT/s) Turbo 1 Core Freq. Core Freq. Rate Freq. Thermal Slot / Design Socket Power Type R32V I5-7600K B-0 6 MB 4 2 0.35 GHz 1.15 GHz 2400 1600 3.8 GHz 4.2 GHz 91 W LGA1151 R32W I5-7400 B-0 6 MB 4 2 0.
Identification Information Pin Count: 1440 Package Size: 42 mm x 28 mm Production (SSPEC): GRP1LINE1 (G1L1): GRP2LINE1: GRP3LINE1 (G3L1): {eX} FPOxxxxxSSPEC Intel logo Table 8. H-Processor Line Processor S-Spec # Processor Step- Cache Number ping Size Func Processor Processor Graphics DDR4 LPDDR3 tional Graphics Graphics Maximum Mem. Mem. Core Cores Freq. Dynamic (MT/s) (MT/s) Turbo 1 Core Freq. Core Freq. Rate Freq.
Summary Tables of Changes Summary Tables of Changes The following table indicates the Specification Changes, Errata, Specification Clarifications or Documentation Changes, which apply to the listed processor stepping. Intel intends to fix some of the errata in a future stepping of the component, and to account for the other outstanding issues through documentation or Specification Changes as noted.
Summary Tables of Changes Errata Summary Table Table 13. Errata Summary Table Processor Line / Stepping KBL-Y Erratum ID KBL-U J-1 (23e) KBL-H KBL-S B-0 B-0 Status Title H-0 H-0 iHDCP2.2 H-0 H-0 iHDCP 2.
Summary Tables of Changes Processor Line / Stepping Erratum ID KBL-Y H-0 KBL-U H-0 iHDCP2.2 H-0 H-0 iHDCP 2.2 J-1 (23e) KBL-H KBL-S B-0 B-0 Status Title KBL013 X X X X X X X No Fix WRMSR to IA32_BIOS_UPDT_TRIG Concurrent With an SMX SENTER/SEXIT May Result in a System Hang KBL014 X X X X X X X No Fix Intel® PT TIP.
Summary Tables of Changes Processor Line / Stepping KBL-Y Erratum ID KBL-U J-1 (23e) KBL-H KBL-S B-0 B-0 Status Title H-0 H-0 iHDCP2.2 H-0 H-0 iHDCP 2.
Summary Tables of Changes Processor Line / Stepping Erratum ID KBL-Y H-0 KBL-U H-0 iHDCP2.2 H-0 H-0 iHDCP 2.
Summary Tables of Changes Processor Line / Stepping KBL-Y Erratum ID KBL-U J-1 (23e) KBL-H KBL-S B-0 B-0 H-0 H-0 iHDCP2.2 H-0 H-0 iHDCP 2.
Summary Tables of Changes Processor Line / Stepping Erratum ID KBL075 KBL076 KBL077 KBL078 KBL-Y KBL-U H-0 H-0 iHDCP2.2 H-0 H-0 iHDCP 2.
Summary Tables of Changes Processor Line / Stepping KBL-Y Erratum ID KBL091 KBL-U H-0 H-0 iHDCP2.2 H-0 H-0 iHDCP 2.2 X X X X J-1 (23e) X KBL-H KBL-S B-0 B-0 X X Status No Fix Title IA32_RTIT_CR3_MATCH MSR Bits[11:5] Are Treated As Reserved Notes: 1. Affects 7th Generation Intel® Core™ i3 U, Intel® Pentium®, Intel® Celeron® Processors. 2. Processor line and Stepping information: – Y-Processor Line stepping H-0: • Without iHDCP2.2 (Mobile) • With iHDCP2.
Errata Errata KBL001 Reported Memory Type May Not Be Used to Access the VMCS and Referenced Data Structures Problem Bits 53:50 of the IA32_VMX_BASIC MSR report the memory type that the processor uses to access the VMCS and data structures referenced by pointers in the VMCS. Due to this erratum, a VMX access to the VMCS or referenced data structures will instead use the memory type that the MTRRs (memory-type range registers) specify for the physical address of the access.
Errata Status For the steppings affected, see the Summary Table of Changes. KBL004 The Corrected Error Count Overflow Bit in IA32_ MC0_STATUS is Not Updated When The UC Bit is Set Problem After a UC (uncorrected) error is logged in the IA32_MC0_STATUS MSR (401H), corrected errors will continue to be counted in the lower 14 bits (bits 51:38) of the Corrected Error Count.
Errata KBL007 x87 FPU Exception (#MF) May be Signaled Earlier Than Expected Problem x87 instructions that trigger #MF normally service interrupts before the #MF. Due to this erratum, if an instruction that triggers #MF is executing when an Enhanced Intel SpeedStep® Technology transitions, an Intel® Turbo Boost Technology transitions, or a Thermal Monitor events occurs, the #MF may be taken before pending interrupts are serviced.
Errata Status For the steppings affected, see the Summary Table of Changes. KBL011 #GP on Segment Selector Descriptor that Straddles Canonical Boundary May Not Provide Correct Exception Error Code Problem During a #GP (General Protection Exception), the processor pushes an error code on to the exception handler’s stack. If the segment selector descriptor straddles the canonical boundary, the error code pushed onto the stack may be incorrect.
Errata Status For the steppings affected, see the Summary Table of Changes. KBL015 Operand-Size Override Prefix Causes 64-bit Operand Form of MOVBE Instruction to Cause a #UD Problem Execution of a 64 bit operand MOVBE instruction with an operand-size override instruction prefix (66H) may incorrectly cause an invalid-opcode exception (#UD). Implication A MOVBE instruction with both REX.W=1 and a 66H prefix will unexpectedly cause an #UD (invalid-opcode exception).
Errata Status For the steppings affected, see the Summary Table of Changes. KBL019 Debug Exceptions May Be Lost or Misreported Following WRMSR to IA32_BIOS_UPDT_TRIG Problem If the WRMSR instruction writes to the IA32_BIOS_UPDT_TRIG MSR (79H) immediately after an execution of MOV SS or POP SS that generated a debug exception, the processor may fail to deliver the debug exception or, if it does, the DR6 register contents may not correctly reflect the causes of the debug exception.
Errata Status For the steppings affected, see the Summary Table of Changes. KBL023 VM Entry That Clears TraceEn May Generate a FUP Problem If VM entry clears Intel® PT (Intel Processor Trace) IA32_RTIT_CTL.TraceEn (MSR 570H, bit 0) while PacketEn is 1 then a FUP (Flow Update Packet) will precede the TIP.PGD (Target IP Packet, Packet Generation Disable). VM entry can clear TraceEn if the VM-entry MSR-load area includes an entry for the IA32_RTIT_CTL MSR.
Errata KBL027 ENCLU[EREPORT] May Cause a #GP When TARGETINFO.MISCSELECT is NonZero Problem The Intel® SGX (Software Guard extensions) ENCLU[EREPORT] instruction may cause a #GP (general protection fault) if any bit is set in TARGETINFO structure’s MISCSELECT field. Implication This erratum may cause unexpected general-protection exceptions inside enclaves. Workaround When executing the ENCLU[EREPORT] instruction, software should ensure the bits set in TARGETINFO.
Errata KBL031 ENCLS[ECREATE] Causes #GP if Enclave Base Address is Not Canonical Problem The ENCLS[ECREATE] instruction uses an SECS (SGX enclave control structure) referenced by the SRCPAGE pointer in the PAGEINFO structure, which is referenced by the RBX register. Due to this erratum, the instruction causes a #GP (generalprotection fault) if the SECS attributes indicate that the enclave should operate in 64bit mode and the enclave base linear address in the SECS is not canonical.
Errata KBL034 DR6.B0-B3 May Not Report All Breakpoints Matched When a MOV/POP SS is Followed by a Store or an MMX Instruction Problem Normally, data breakpoints matches that occur on a MOV SS, r/m or POP SS will not cause a debug exception immediately after MOV/POP SS but will be delayed until the instruction boundary following the next instruction is reached. After the debug exception occurs, DR6.
Errata Implication Performance monitoring with the instruction-retired event may over count by up to four extra events per instance of WRMSR which targets the IA32_BIOS_UPDT_TRIG register. Workaround None identified. Status For the steppings affected, see the Summary Table of Changes.
Errata Workaround It is possible for the BIOS to contain a workaround Status For the steppings affected, see the Summary Table of Changes. KBL041 Intel® PT Buffer Overflow May Result in Incorrect Packets Problem Under complex micro-architectural conditions, an Intel PT (Processor Trace) OVF (Overflow) packet may be issued after the first byte of a multi-byte CYC (Cycle Count) packet, instead of any remaining bytes of the CYC.
Errata KBL044 Execution of VAESENCLAST Instruction May Produce a #NM Exception Instead of a #UD Exception Problem Execution of VAESENCLAST with VEX.L= 1 should signal a #UD (Invalid Opcode) exception, however, due to the erratum, a #NM (Device Not Available) exception may be signaled. Implication As a result of this erratum, an operating system may restore AVX and other state unnecessarily. Workaround None identified. Status For the steppings affected, see the Summary Table of Changes.
Errata Status For the steppings affected, see the Summary Table of Changes. KBL048 PECI Frequency Limited to 1 MHz Problem The PECI (Platform Environmental Control Interface) 3.1 specification’s operating frequency range is 0.2 MHz to 2 MHz. Due to this erratum, PECI may be unreliable when operated above 1 MHz. Implication Platforms attempting to run PECI above 1 MHz may not behave as expected. Workaround None identified. Platforms should limit PECI operating frequency to 1 MHz.
Errata KBL052 Integrated Audio Codec May Not be Detected Problem Integrated Audio Codec may lose power when LPSP (Low-Power Single Pipe) mode is enabled for an eDP* (embedded DisplayPort) or DP/HDMI ports. Platforms with Intel® SST (Intel® Smart Sound Technology) enabled are not affected. Implication The Audio Bus driver may attempt to do enumeration of Codecs when eDP or DP/HDMI port enters LPSP mode, due to this erratum, the Integrated Audio Codec will not be detected and audio maybe be lost.
Errata KBL056 CTR_FRZ May Not Freeze Some Counters Problem IA32_PERF_GLOBAL_STATUS.CTR_FRZ (MSR 38EH, bit 59) is set when either (1) IA32_DEBUGCTL.FREEZE_PERFMON_ON_PMI (MSR 1D9H, bit 12) is set and a PMI is triggered, or (2) software sets bit 59 of IA32_PERF_GLOBAL_STATUS_SET (MSR 391H). When set, CTR_FRZ should stop all core performance monitoring counters from counting. However, due to this erratum, IA32_PMC4-7 (MSR C5-C8H) may not stop counting.
Errata KBL059 Instructions Fetch #GP After RSM During Inter® PT May Push Incorrect RFLAGS Value on Stack Problem If Intel PT (Processor Trace) is enabled, a #GP (General Protection Fault) caused by the instruction fetch immediately following execution of an RSM instruction may push an incorrect value for RFLAGS onto the stack. Implication Software that relies on RFLAGS value pushed on the stack under the conditions described may not work properly. Workaround None identified.
Errata KBL063 Performance Monitoring Counters May Undercount When Using CPL Filtering Problem Performance Monitoring counters configured to count only OS or only USR events by setting exactly one of bits 16 or 17 in IA32_PERFEVTSELx MSRs (186H-18DH) may not count for a brief period during the transition to a new CPL. Implication A measurement of ring transitions (using the edge-detect bit 18 in IA32_PERFEVTSELx) may undercount, such as CPL_CYCLES.RING0_TRANS (Event 5CH, Umask 01H).
Errata KBL067 PEBS EventingIP Field May Be Incorrect Under Certain Conditions Problem The EventingIP field in the PEBS (Processor Event-Based Sampling) record reports the address of the instruction that triggered the PEBS event. Under certain complex microarchitectural conditions, the EventingIP field may be incorrect. Implication When this erratum occurs, performance monitoring software may not attribute the PEBS events to the correct instruction. Workaround None identified.
Errata KBL071 HWP’s Maximum_Performance Value is Reset to 0xFF Problem According to HWP (Hardware P-states) specification, the reset value of the Maximum_Performance field (bits [15:8]) in IA32_HWP_REQUEST MSR (774h) should be set to the value of IA32_HWP_CAPABILITIES MSR (771H) Highest_Performance field (bits[7:0]) after reset. Due to this erratum, the reset value of Maximum_Performance is always set to 0xFF. Implication Software may see an unexpected value in Maximum Performance field.
Errata MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS event D2H, umask 01H MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT event D2H, umask 02H MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM event D2H, umask 04H MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE event D2H, umask 08H Implication The listed performance monitoring events may produce incorrect results including PEBS records generated at an incorrect point Workaround None identified Status For the steppings affected, see the Summary Table of Changes.
Errata Implication Due to this erratum, the CPU may hang on the execution of VMASKMOV Workaround It is possible for the BIOS to contain a workaround for this erratum. Status For the steppings affected, see the Summary Table of Changes. KBL078 PECI May Not be Functional After Package C10 Resume Problem When resuming from Package C10, PECI may fail to function properly. Implication When this erratum occurs, the PECI does not respond to any command.
Errata KBL082 BNDLDX And BNDSTX May Not Signal #GP on Non-Canonical Bound Directory Access Problem BNDLDX and BNDSTX instructions access the bound’s directory and table to load or store bounds. These accesses should signal #GP (general protection exception) when the address is not canonical (i.e. bits 48 to 63 are not the sign extension of bit 47).
Errata KBL086 EDRAM Corrected Error Events May Not be Properly Logged After a Warm Reset Problem After a warm reset, an EDRAM corrected error may not be logged correctly until the associated machine check register is initialized. This erratum may affect IA32_MC8_STATUS or IA32_MC10_STATUS. Implication The EDRAM corrected error information may be lost when this erratum occurs.
Errata Implication Software resuming from system sleep states S3 or S4 and relying on receiving a page fault from the above enclave accesses may not operate properly. Workaround Software can monitor #GP faults to detect that an enclave has been destroyed and needs to be rebuilt after resuming from S3 or S4 Status For the steppings affected, see the Summary Table of Changes.
Specification Changes Specification Changes There are no Specification Changes in this Specification Update revision.
Specification Clarifications Specification Clarifications There are no specification clarifications in this Specification Update revision.
Documentation Changes Documentation Changes There are no documentation changes in this Specification Update revision.
