Specification Sheet

Datasheet, Volume 1 of 2 55
Electrical Specifications
5.5.2.6 Serial VID Interface (SVID) DC Specifications
Symbol Parameter Min Nom Max Units Notes
5.5.2.7 Processor Asynchronous Sideband DC Specifications
I
IL Input Leakage Current Signals ±50 ±200 μA
SR Output Edge Rate (50 ohm to
V
CCIO) Signal:
BPM_N[7:0], PRDY_N, TDO
1.13 5 V/ns
1
Notes:
1. These are measured between V
IL
and V
IH
.
2. The signal edge rate must be met or the signal must transition monotonically to the asserted state.
V
CCIO CPU I/O Voltage
V
CCIO
- 5%
1.0
V
CCIO
+ 5%
V1
V
IL Input Low Voltage Signals SVIDDATA,
SVIDALERT_N
——
0.3*V
CCIO V
1
V
IH Input High Voltage Signals SVIDDATA,
SVIDALERT_N
0.7*V
CCIO —— V
1
V
OL Output Low Voltage Signals: SVIDCLK,
SVIDDATA
——
0.2*V
CCIO V
1, 6
V
Hysteresis Hysteresis
0.1*V
CCIO —— V1
R
ON Buffer On Resistance Signals SVIDCLK,
SVIDDATA
14 — 4 
2
I
IL Input Leakage Current ±50 — ±200 μA 3, 4
Input Edge Rate Signal: SVIDALERT_N 0.05 — — V/ns 5
Output Edge Rate 1.13 — 5 V/ns 5, 6
Notes:
1.
V
CCIO refers to instantaneous
V
CCIO.
2. Measured at 0.31*
V
CCIO.
3. Vin between 0V and
V
CCIO (applies to SVIDDATA and SVIDALERT_N only).
4. N/A
5. These are measured between V
IL
and V
IH
.
6. Value obtained through test bench with 50 ohms pull-up to
V
CCIO.
Symbol Parameter Min Max Units Notes
CMOS input buffers
V
IL Input Low Voltage — 0.3
*V
CCIO V 1, 2, 4
V
IH Input High Voltage 0.7
*V
CCIO — V 1, 2, 4
V
Hysteresis Hysteresis Signals 0.1
*V
CCIO — V 1,2, 4
SRI Input Slew Rate 0.005 — V/ns
SR2 Input Slew Rate: PMSYNC 0.05 — V/ns
Open Drain Output buffers
I
L
Input Leakage Current ±50 ±200 μA 1, 2, 4
Symbol Parameter Min Max Units Notes