Specification Sheet
4 Datasheet, Volume 1 of 2
4.3 Direct Media Interface 3 (DMI3) Signals............................................................... 29
4.4 PECI Signal ...................................................................................................... 30
4.5 System Reference Clock Signals.......................................................................... 30
4.6 JTAG and TAP Signals........................................................................................ 30
4.7 Serial VID Interface (SVID) Signals ..................................................................... 31
4.8 Processor Asynchronous Sideband and Miscellaneous Signals.................................. 31
4.9 Processor Power and Ground Supplies ................................................................. 34
5 Electrical Specifications .......................................................................................... 35
5.1 Integrated Voltage Regulation ............................................................................ 35
5.2 Processor Signaling ........................................................................................... 35
5.2.1 System Memory Interface Signal Groups................................................... 35
5.2.2 PCI Express* Signals.............................................................................. 35
5.2.3 DMI3/PCI Express* Signals ..................................................................... 35
5.2.4 Platform Environmental Control Interface (PECI) ........................................ 36
5.2.4.1 Input Device Hysteresis............................................................. 36
5.2.5 System Reference Clocks (BCLK{0/1/2}_DP, BCLK{0/1/2}_DN) .................. 36
5.2.6 JTAG and Test Access Port (TAP) Signals................................................... 37
5.2.7 Processor Sideband Signals ..................................................................... 37
5.2.8 Power, Ground and Sense Signals ............................................................ 37
5.2.8.1 Power and Ground Lands........................................................... 37
5.2.8.2 Decoupling Guidelines ............................................................... 38
5.2.8.3 Voltage Identification (VID) ....................................................... 38
5.2.8.4 SVID Commands ...................................................................... 38
5.2.8.5 SetWP Working Point Command ................................................. 39
5.2.8.6 SetVID Fast Command .............................................................. 39
5.2.8.7 SetVID Slow ............................................................................ 40
5.2.8.8 SetVID Decay .......................................................................... 40
5.2.8.9 SVID Voltage Rail Addressing ..................................................... 40
5.2.9 Reserved or Unused Signals .................................................................... 42
5.3 Signal Group Summary...................................................................................... 42
5.3.1 Power-On Configuration (POC) Options ..................................................... 45
5.4 Absolute Maximum and Minimum Ratings............................................................. 46
5.4.1 Storage Conditions Specifications............................................................. 46
5.5 DC Specifications .............................................................................................. 47
5.5.1 Voltage and Current Specifications ........................................................... 47
5.5.2 Signal DC Specifications.......................................................................... 50
5.5.2.1 DDR4 Signal DC Specifications ................................................... 50
5.5.2.2 PECI DC Specifications .............................................................. 52
5.5.2.3 System Reference Clock (BCLK{0/1/2}) DC Specifications ............. 52
5.5.2.4 SMBus DC Specifications ........................................................... 54
5.5.2.5 JTAG and TAP Signals DC Specifications ...................................... 54
5.5.2.6 Serial VID Interface (SVID) DC Specifications............................... 55
5.5.2.7 Processor Asynchronous Sideband DC Specifications ..................... 55
5.5.2.8 Miscellaneous Signals DC Specifications ...................................... 56